Integrated I/O Remapping mechanism

A computer readable medium storing:

• a first one or more instructions to establish an address range within a memory map, wherein addresses within the address range are to be mapped to other addresses within the memory map through an address relocation table;
• a second one or more instructions to configure a graphics device to use a first portion of the address range for accesses to memory;
• and
• a third one or more instructions to configure one or more peripheral devices to use a second portion of the address range for accesses to memory, wherein the one or more peripheral devices are different from the graphics device.

A computer system comprising:

• one or more address relocation caches configured to store mappings between addresses within an address range of a memory map and other addresses within the memory map;
• a graphics device configured to access a first portion of the address range;
• and
• one or more peripheral devices configured to access a second portion of the address range;
• wherein the one or more address relocation caches are coupled to receive addresses from the graphics device and the peripheral devices and to provide corresponding addresses outside of the address range if the addresses received from the graphics device and the peripheral devices are within the address range, the one or more address relocation caches providing the corresponding addresses responsive to the stored mappings.

A computer system comprising:

• at least one translation circuit configured to translate addresses within an address range of a memory map according to translations stored in an address relocation table;
• a graphics device configurable to access a first portion of the address range;
• and
• at least one peripheral device configurable to access a second portion of the address range;
• wherein the address range is below a predetermined limit in the memory map and the second portion of the address range is mapped to other addresses above the predetermined limit by the at least one translation circuit responsive to the translations in the address relocation table during use.

A method comprising:

• establishing an address range within a memory map, the address range to be mapped through an address relocation table;
• configuring a graphics device to use a first portion of the address range for access to memory;
• and
• configuring at least one peripheral device to use a second portion of the address range to access memory above a predetermined limit, wherein the address range is below the predetermined limit and the second portion of the address range is mapped to other addresses above the predetermined limit through the address relocation table.

A computer readable medium storing a plurality of instructions which, when executed, implement a method comprising:

• establishing an address range within a memory map, the address range to be mapped through an address relocation table;
• configuring a graphics device to use a first portion of the address range for access to memory;
• and
• configuring at least one peripheral device to use a second portion of the address range to access memory above a predetermined limit, wherein the address range is below the predetermined limit and the second portion of the address range is mapped to other addresses above the predetermined limit through the address relocation table.