Input common-mode voltage feedback circuit for continuous-time sigma-delta analog-to-digital converter
AssigneeAnalog Devices, Inc.
InventorKhiem Nguyen
Life of this patent
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Abstract
A novel circuit is used to monitor the common-mode voltage at the summing junctions of the first integrator in a continuous-time ΣΔ ADC, wherein the circuit produces a control voltage which adjusts the quiescent current of the feedback DAC to compensate for any common-mode offset current. Since the adjustment takes place within the feedback DAC, there is no extra noise added to the differential signal path. The implementation provides for no degradation to the SNR of the converter.
Claims26
A method of partitioning a feedback DAC in a continuous-time sigma-delta analog-to-digital converter, said method comprising the steps of:
- including at least a portion of said feedback DAC in a negative feedback loop;
- and
- stabilizing an input common mode (CM) voltage at the summing junctions of a continuous-time integrator via said negative feedback loop, wherein said continuous-time integrator is part of said continuous-time sigma-delta analog-to-digital converter.
A method of partitioning a feedback DAC in a continuous-time sigma-delta analog-to-digital converter comprising, in a first stage, a continuous-time integrator and said feedback DAC, said method comprising the steps of:
- including at least a portion of said feedback DAC in a negative feedback loop;
- and
- monitoring an input common mode (CM) voltage at the summing junctions of said continuous-time integrator;
- and
- generating a control voltage that adjusts the circuit generating a quiescent current of said feedback DAC based on said monitored CM voltage.
A method of partitioning a feedback DAC in a continuous-time sigma-delta analog-to-digital converter, said method comprising the steps of
- including a non-input signal dependent portion of said feedback DAC in a negative feedback loop;
- and
- correcting a quiescent current of said feedback DAC or an input CM offset current of an integrator, or both, via said negative feedback loop, wherein said integrator is part of said continuous-time sigma-delta analog-to-digital converter.
A method to adjust the bias voltages of a feedback DAC in a continuous-time sigma-delta analog-to-digital converter, said method comprising:
- including at least a portion of said feedback DAC in a negative feedback loop;
- and
- stabilizing an input common mode (CM) voltage of a continuous-time integrator that is part of said continuous-time sigma-delta analog-to-digital converter via said negative feedback loop, wherein bias voltages of said feedback DAC are changed to stabilize said CM voltage.
An amplifier embedded in a negative feedback loop in a continuous-time sigma-delta analog-to-digital converter, said continuous-time sigma-delta analog-to-digital converter comprising, in a first state, a continuous-time integrator and a feedback DAC, said amplifier comprising:
- an input means SJP receiving positive summing junction voltage;
- an input means SJN receiving negative summing junction voltage;
- an input means VREF receiving a reference voltage;
- an output means adjusting a quiescent current of said feedback DAC, wherein said amplifier monitors an input common mode (CM) voltage at the summing junctions of said continuous-time integrator and generates a control voltage that adjusts said quiescent current of said feedback DAC based on said monitored CM voltage.
Dependencies are inferred from the claim text.