PLL employing a sample-based capacitance multiplier

A phase-locked loop (PLL) comprising:

• a phase detector (PD) adapted to generate an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• a proportional charge pump adapted to generate a first voltage for a first time period based on the up/down signal;
• an integral charge pump adapted to generate a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• and a voltage-controlled oscillator (VCO) adapted to generate the clock signal based upon a combination of the first and second voltages;
• wherein the VCO comprises an inductor-capacitor (LC) oscillator, the combination of the first and second voltages setting a first portion of the LC oscillator capacitance, and a third voltage setting a second portion of the LC oscillator capacitance.

A phase-locked loop (PLL) comprising:

• a phase detector (PD) adapted to generate an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• a proportional charge pump adapted to generate a first voltage for a first time period based on the un/down signal;
• an integral charge pump adapted to generate a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• and a voltage-controlled oscillator (VCO) adapted to generate the clock signal based upon a combination of the first and second voltages;
• wherein the integral charge pump comprises a return-to-zero charge pump.

A phase-locked loop (PLL) comprising:

• a phase detector (PD) adapted to generate an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• a proportional charge pump adapted to generate a first voltage for a first time period based on the up/down signal;
• an integral charge pump adapted to generate a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• and a voltage-controlled oscillator (VCO) adapted to generate the clock signal based upon a combination of the first and second voltages;
• wherein the proportional charge pump comprises a non-return-to-zero charge pump.

A phase-locked loop (PLL) comprising:

• a phase detector (PD) adapted to generate an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• a proportional charge pump adapted to generate a first voltage for a first time period based on the up/down signal;
• an integral charge pump adapted to generate a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• and a voltage-controlled oscillator (VCO) adapted to generate the clock signal based upon a combination of the first and second voltages;
• further comprising a phase-frequency detector and a multiplexer (MUX), wherein:
• the phase-frequency detector is adapted to:
• 1) compare the clock signal and a reference signal,
• 2) generate a switch signal based on the comparison of the clock signal and the reference signal, and
• 3) generate a phase difference between the clock signal and the reference signal;
• and
• the MUX is adapted to select either i) the up/down signal or ii) the phase difference between the clock signal and the reference signal as an input to the proportional and integral charge pumps,
• wherein the proportional and integral charge pumps generate the first and second voltages based upon the phase difference between the clock signal and the reference signal when selected as the input by the MUX.

A method of implementing a phase-locked loop (PLL) comprising the steps of:

• (a) generating, by a phase detector (PD), an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• (b) generating a first voltage for a first time period based on the up/down signal;
• and
• (c) generating a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• (d) combining the first and second voltages;
• and
• (e) generating, with a voltage-controlled oscillator (VCO), the clock signal based upon the combination of the first and second voltages;
• wherein, for step (a), the phase detector is a bang-bang phase detector.

A method of implementing a phase-locked loon (PLL) comprising the steps of:

• (a) generating, by a phase detector (PD), an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• (b) generating a first voltage for a first time period based on the up/down signal;
• and
• (c) generating a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• (d) combining the first and second voltages;
• and
• (e) generating, with a voltage-controlled oscillator (VCO), the clock signal based upon the combination of the first and second voltages;
• wherein, for step (e), the VCO comprises an inductor-capacitor (LC) oscillator, and step (d) comprises the steps of (d1) setting a first portion of the LC oscillator capacitance based on the combination of the first and second voltages, (d2) generating a third voltage, and (d3 ) setting a second portion of the LC oscillator capacitance based on the third voltage.

A method of implementing a phase-locked loop (PLL) comprising the steps of:

• (a) generating, by a phase detector (PD), an up/down signal based on a phase difference between a data signal and a clock signal input to the PD, wherein the phase error is generated by sampling of the clock signal by the data signal;
• (b) generating a first voltage for a first time period based on the up/down signal;
• and
• (c) generating a second voltage for a second time period across a capacitor based upon the capacitance of the capacitor, a truncated version of the up/down signal, and a sampling rate of the data by the PD, wherein the second time period is less than the first time period;
• (d) combining the first and second voltages;
• and
• (e) generating, with a voltage-controlled oscillator (VCO), the clock signal based upon the combination of the first and second voltages;
• further comprising the steps of:
• comparing the clock signal and a reference signal,
• generating a switch signal based on the comparison of the clock signal and the reference signal, and
• generating a phase difference between the clock signal and the reference signal;
• and
• selecting either i) the up/down signal or ii) the phase difference between the clock signal and the reference signal as an input to the proportional and integral charge pumps, and
• wherein the first and second voltages are generated based upon the phase difference between the clock signal and the reference signal when selected as the input by the MUX.