Linear multiplier circuit
AssigneeVIA Technologies, Inc.
InventorWei-shang Chu
Life of this patent
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AssigneeVIA Technologies, Inc.
InventorWei-shang Chu
Estimating the term…
A linear multiplier circuit comprises a first, a second, a third and a fourth transistor, each having a drain, a source, a gate and substantially an identity threshold voltage. Each of these four transistors operates with a fixed drain-to-source voltage applied between the drain and source, a gate-to-source voltage applied between the gate and source. The sources of the first and second transistors, and the drains of the third and fourth transistors are coupled to form the output terminal. The gate-to-source voltages of the first, second, third and fourth transistor are respectively the sum of the first and second input signals, an additionally introduced input signal, and the identity threshold voltage; the sum of the additionally introduced input signal and the identity threshold voltage; the sum of the first input signal, the additionally introduced input signal and the identity threshold voltage; and the sum of the second input signal, the additionally introduced input signal and the identity threshold voltage.
A linear multiplier circuit, receiving a first input signal and a second input signal, generating a current proportional to a product of the first and second input signals on an output terminal of the linear multiplier circuit, the linear multiplier circuit comprising:
A linear multiplier circuit, receiving a first input signal and a second input signal, generating a current proportional to a product of the first and second input signals on an output terminal of the linear multiplier circuit, wherein the linear multiplier circuit comprises:
A method for generating a product of a first input signal and a second input signal in a multiplier circuit, comprising:
Dependencies are inferred from the claim text.