US 7,009,441 B2Granted

Phase multiplier circuit

OwnerAlan Fiedlerinventor

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Abstract

So as to generate multiple output signals whose phases are evenly spaced about 360 degrees, and having a frequency equal to that of an input signal, a phase multiplier circuit includes three or more instances of a phase multiplier subcircuit and additional circuitry configured in a negative feedback loop. Each phase multiplier subcircuit includes a difference circuit, a loop filter transistor, and a voltage-controlled delay circuit. The difference circuit converts to a phase current a delay from an input signal to the delay circuit to an output signal from the delay circuit, and subtracts from the phase current a bias current proportional to the smallest positive delay from the output signal with the largest phase to the output signal with the smallest phase. The subtracted current is integrated by the loop filter transistor, and steady-state operation is achieved when for each phase multiplier subcircuit, the bias current is equal to the phase current. Evenly spaced phases of the output signals about 360 degrees are achieved when the delay to phase current gain and delay to bias current gain are substantially equal.

Claims14

Dependent claims

A phase multiplier subcircuit, comprising:

first and second subcircuit power supply terminals;
a PULLUPBIAS subcircuit terminal;
a COMMON subcircuit terminal;
INA and /INB subcircuit terminals;
OUTA, /OUTB, and OUTB subcircuit terminals;
a first dual-gate transistor having a single drain, a first gate coupled to the OUTB subcircuit terminal, a second gate coupled to the /INB subcircuit terminal, and a single source coupled to the COMMON subcircuit terminal;
a first transistor having a gate and a drain coupled to the single drain of the first dual-gate transistor, and a source coupled to the first subcircuit power supply terminal;
a second transistor having a drain coupled to a BIASP integration node, a gate coupled to the gate of the first transistor, and a source coupled to the first subcircuit power supply terminal;
a third transistor having a drain coupled to the BIASP node, a gate coupled to the PULLUPBIAS subcircuit terminal, and a source coupled to the second subcircuit power supply terminal;
a fourth transistor having a drain coupled to a BIASN node, a gate coupled to the BIASP node, and a source coupled to the second subcircuit power supply terminal;
a fifth transistor having a gate and a drain coupled to the BIASN node, and a source coupled to the first subcircuit power supply terminal;
a second dual-gate transistor having a single drain, a first gate coupled to the BIASP node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the second subcircuit power supply terminal;
a third dual-gate transistor having a single drain coupled to the single drain of the second dual-gate transistor, a first gate coupled to the BIASN node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the first subcircuit power supply terminal;
a fourth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASP node, a second gate coupled to the single drain of the third dual-gate transistor, and a single source coupled to the second subcircuit power supply terminal;
a fifth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASN node, a second gate coupled to the drain of the third dual-gate transistor, and a single source coupled to the first subcircuit power supply terminal;
a first inverter having an output terminal coupled to the /OUTB subcircuit terminal, and an input terminal coupled to the OUTA subcircuit terminal;
and
a second inverter having an output terminal coupled to the OUTB subcircuit terminal, and an input terminal coupled to the /OUTB subcircuit terminal.

15 more elements

A phase multiplier circuit comprising:

first and second power supply terminals;
an input signal terminal;
first, second, third, and fourth output terminals;
a COMMON node;
a PULLUPBIAS node;
a first inverter having an output terminal, and an input terminal coupled to the input signal terminal;
a second inverter having an output terminal coupled to the first output terminal, and an input terminal coupled to the output terminal of the first inverter;
a plurality of phase multiplier subcircuits, each comprising:
first and second subcircuit power supply terminals;
a PULLUPBIAS subcircuit terminal;
a COMMON subcircuit terminal;
INA and /INB subcircuit terminals;
OUTA, /OUTB, and OUTB subcircuit terminals;
a first dual-gate transistor having a single drain, a first gate coupled to the OUTB subcircuit terminal, a second gate coupled to the /INB subcircuit terminal, and a single source coupled to the COMMON subcircuit terminal;
a first transistor having a gate and a drain coupled to the single drain of the first dual-gate transistor, and a source coupled to the first subcircuit power supply terminal;
a second transistor having a drain coupled to a BIASP integration node, a gate coupled to the gate of the first transistor, and a source coupled to the first
subcircuit power supply terminal;
a third transistor having a drain coupled to the BIASP node, a gate coupled to the PULLUPBIAS subcircuit terminal, and a source coupled to the second subcircuit power supply terminal;
a fourth transistor having a drain coupled to a BIASN node, a gate coupled to the BIASP node, and a source coupled to the second subcircuit power supply terminal;
a fifth transistor having a gate and a drain coupled to the BIASN node, and a source coupled to the first subcircuit power supply terminal;
a second dual-gate transistor having a single drain, a first gate coupled to the BIASP node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the second subcircuit power supply terminal;
a third dual-gate transistor having a single drain coupled to the single drain of the second dual-gate transistor, a first gate coupled to the BIASN node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the first subcircuit power supply terminal;
a fourth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASP node, a second gate coupled to the single drain of the third dual-gate transistor, and a single source coupled to the second subcircuit power supply terminal;
a fifth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASN node, a second gate coupled to the drain of the third dual-gate transistor, and a single source coupled to the first subcircuit power supply terminal;
a first inverter having an output terminal coupled to the /OUTB subcircuit terminal, and an input terminal coupled to the OUTA subcircuit terminal;
and
a second inverter having an output terminal coupled to the OUTB subcircuit terminal, and an input terminal coupled to the /OUTB subcircuit terminal;
a first one of the plurality of phase multiplier subcircuits wherein:
the first subcircuit power supply terminal is coupled to the first power supply terminal;
the second subcircuit power supply terminal is coupled to the second power supply terminal;
the PULLUPBIAS subcircuit terminal is coupled to the PULLUPBIAS node;
the COMMON subcircuit terminal is coupled to the COMMON node;
the INA subcircuit terminal is coupled to the input signal terminal;
the /INB subcircuit terminal is coupled to the first inverter's output terminal;
and
the OUTB subcircuit terminal is coupled to the second output terminal;
a second one of the plurality of phase multiplier subcircuits wherein:
the first subcircuit power supply terminal is coupled to the first power supply terminal;
the second subcircuit power supply terminal is coupled to the second power supply terminal;
the PULLUPBIAS subcircuit terminal is coupled to the PULLUPBIAS node;
the COMMON subcircuit terminal is coupled to the COMMON node;
the INA subcircuit terminal is coupled to the first phase multiplier subcircuit's OUTA terminal;
the /INB subcircuit terminal is coupled to the first phase multiplier subcircuit's /OUTB terminal;
and
the OUTB subcircuit terminal is coupled to the third output terminal;
a third one of the plurality of phase multiplier subcircuits wherein:
the first subcircuit power supply terminal is coupled to the first power supply terminal;
the second subcircuit power supply terminal is coupled to the second power supply terminal;
the PULLUPBIAS subcircuit terminal is coupled to the PULLUPBIAS node;
the COMMON subcircuit terminal is coupled to the COMMON node;
the INA subcircuit terminal is coupled to the second phase multiplier subcircuit's OUTA terminal;
the /INB subcircuit terminal is coupled to the second phase multiplier subcircuit's /OUTB terminal;
and
the OUTB subcircuit terminal is coupled to the fourth output terminal;
a sixth dual-gate transistor having a single drain coupled to a second node, a first gate coupled to the first output terminal, a second gate coupled to the third phase multiplier's /OUTB terminal, and a single source coupled to the COMMON node;
a sixth transistor having a gate and a drain coupled to the second node, and a source coupled to the first power supply terminal;
a seventh transistor having a drain coupled to the PULLUPBIAS node, a gate coupled to the gate of the sixth transistor, and a source coupled to the first power supply terminal;
and
an eighth transistor having a gate and a drain coupled to the PULLUPBIAS node, and a source coupled to the second power supply terminal.

56 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/775,310Filed 10 Feb 2004
Published: US 2005/0174160 A111 Aug 2005
Granted: 7 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 5/1504
With asynchronously driven series connected output stages: using a chain of active delay devices
H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used
H03K 2005/00286
Manipulating of pulses not covered by one of the other main groups of this subclass: phase shifter, i.e. the delay between the output and input…
H03K
Pulse technique