Circuit and method for generating internal clock signal

A circuit for generating an internal clock signal, comprising:

• an operating frequency decision unit for determining whether an external clock signal is a low frequency or a high frequency depending on a column address strobe (CAS) latency and outputting an detecting signal;
• an internal clock signal generator for waveform-shaping the external clock signal and generating an internal clock signal depending on the detecting signal of the operating frequency decision unit, or generating the external clock signal as the internal clock signal as it is, the internal clock signal generator comprising:
• a delay unit for delaying the external clock signal by some time;
• and
• a pulse-shaping unit for logically combining the external clock signal with the output of the delay unit and generating the internal clock signal depending on the output detecting signal of the operating frequency decision unit, or generating the external clock signal as the internal clock signal as it is, the pulse-shaping unit comprising a first NAND gate for logically combining the external clock signal with the output signal of the delay unit depending on the detecting signal of the operating frequency decision unit, a second NAND gate into which the external clock signal and the output signal of the first NAND gate are inputted, and an inverter for inverting the output signal of the second NAND gate.

A method of generating an internal clock signal, comprising the steps of:

• determining whether an external clock signal is a low frequency or a high frequency depending on a column address strobe (CAS) latency;
• and
• waveform-shaping the external clock signal and generating an internal clock signal depending on a result of the determination step, or generating the external clock signal as the internal clock signal as it is,
• wherein the CAS latency has a value of 0 to 7 and the external clock signal is determined as the high frequency if the value of the CAS latency is over 4.

A method of generating an internal clock signal, comprising the steps of:

• determining whether an external clock signal is a low frequency or a high frequency depending on a column address strobe (CAS) latency;
• generating a delayed external clock signal by delaying the external clock signal by some time;
• and
• waveform-shaping the external clock signal using the delayed external clock signal and generating an internal clock signal depending on a result of the determination step, or generating the external clock signal as the internal clock signal as it is,
• wherein the step of generating the clock comprises the steps of:
• waveform-shaping the external clock signal by logically combining the external clock signal with the delayed external clock signal and generating the internal clock signal if the external clock signal is the low frequency;
• and
• generating the external clock signal as the internal clock signal as it is if the external clock signal is the high frequency.