Trans-admittance trans-impedance logic for integrated circuits
AssigneeLucent Technologies Inc.
InventorsRajasekhar Pullela, Mario Reinhold
Life of this patent
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Abstract
A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.
Claims19
A latch comprising:
- a clocked trans-admittance stage circuit for producing a current output responsive to an input voltage;
- and
- an active load connected to receive input data and said current output as input and produce a voltage output that is received by said clocked trans-admittance stage circuit to control at least one element thereof to provide a data output.
A cascaded latch chain comprising:
- a clocked trans-admittance stage latch configured to produce an output current responsive to an input voltage;
- and
- at least one latch pair configured to receive an input data and the output current and provide a voltage output to control at least one element of said clocked trans-admittance stage latch to provide a data output.
A latch pair comprising:
- a first combined trans-admittance and trans-impedance stage coupled to an independently clocked second combined trans-admittance and trans-impedance stage, wherein each of said first and said second combined stages have an input and an output, and at least one of said combined trans-admittance and trans-impedance stages has a clocked trans-admittance stage circuit for producing a current output responsive to an input voltage;
- and
- an active load configured to receive input data and said current output and produce a voltage output that is received by said clocked trans-admittance stage circuit to control at least one element thereof to provide a data output.
Dependencies are inferred from the claim text.