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US 7,009,437 B2Granted
Smart buffer circuit to match a delay over a range of loads
AssigneeIntel Corporation
InventorsThomas D. Fletcher, Javed S. Barkatullah
Life of this patent
Estimating the term…
Abstract
A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.
Claims10
A circuit comprising:
- an input to receive an input clock signal;
- an output to provide an output clock signal having a corrected duty cycle;
- a reset path between the input and the output, the reset path to control a width of the output clock signal;
- a feedback path between the output and the reset path to control a delay of the reset path to correct the duty cycle of the output clock signal;
- smart buffer circuitry coupled between the input and the output, the smart buffer circuitry being capable of adjusting the output signal to provide for proper duty cycle correction for a range of loads to be coupled to the output;
- and
- frequency multiplying circuitry coupled to between the input and the output, the frequency multiplying circuitry to multiply the frequency of the output clock signal relative to the input clock signal.
4 more elements
An apparatus comprising:
- a first circuit including an output driver, the first circuit to provide a first output signal at the output driver, the output driver including a fixed number of devices;
- and
- a smart buffer circuit to match a delay of the first output signal to a delay of a reference signal independent of a load coupled to the first circuit over a range of load values, the smart buffer circuit to adjust the delay of the output signal by adjusting the drive strength of the output driver;
- and
- a first phase detector to detect a difference in delay between one of a rising or falling edge of the first output signal and a corresponding edge of the reference signal, the first phase detector to provide a first reference control signal at an output, the first reference control signal to control a delay of a first delay element in the first circuit to adjust the drive strength of the driver for a first value of an input signal to the first circuit.
2 more elements
Dependencies are inferred from the claim text.