Pulsewidth control loop device with complementary signals

A free-skew mutual-correlated pulsewidth control loop circuit, comprising:

• a control stage circuit, one end of which being coupled with a control signal and a clock signal and another end of said control stage circuit outputting an output signal;
• a buffer chain, one end of which being coupled with another end of said control stage for receiving said output signal of said control stage circuit and another end of said buffer chain generating another output signal;
• a complementary circuit, one end of which being coupled with said another end of said buffer chain for receiving said another output signal of said buffer chain and another end of said complementary circuit outputting a pair of complementary output signals;
• a phase blending circuit, one end of which being respectively coupled with said pair of complementary output signals of said complementary circuit for generating two complementary phase blending signals to be outputted from another end;
• two charge pumps, one end of each being coupled with said output signal of said phase blending circuit respectively and another end of said two charge pumps generating a charge pump output signal respectively;
• a decoupling capacitor, two ends of which being coupled with said another end of said two charge pumps;
• and
• a comparator, one end of which being respectively coupled with said charge pump output signal of each of said two charge pumps and another end of said comparator outputting said control signal, feedback said control signal to said control stage circuit at the same time.

A mutual-correlated pulsewidth control loop circuit device with system-on-chip (SOC) inserted, comprising:

• a control stage circuit, one end of which being coupled with a control signal and a clock signal and another end of said control stage circuit outputting a output signal;
• a buffer chain, one end of which being coupled with said another end of said control stage circuit for receiving said output signal of said control stage circuit and another end of said buffer chain outputting another output signal;
• a complementary circuit, one end of which being coupled with said another end of said buffer chain for receiving said output signal of said buffer chain and another end of said complementary circuit outputting a pair of complementary output signals;
• two charge pumps, one end of each being coupled with said pair of complementary output signals of said complementary circuit respectively and another end of said two charge pumps generating a charge pump output signal respectively;
• a comparator, one end of which being respectively coupled with said charge pump output signal of each of said two charge pumps and another end of said comparator outputting said control signal, feedback said control signal to said control stage circuit at the same time;
• and
• a system-on-chip, receiving said pair of complementary output signals outputted by said complementary circuit.