US 7,009,435 B2Granted

Output buffer with controlled slew rate for driving a range of capacitive loads

AssigneeNano Silicon Pte. Ltd.

InventorsJun Ho Cho, Hong Sair Lim

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Abstract

Output buffer slew rate variation over variations in load capacitance is minimized by dividing output voltage transitions into distinct time and output current segments. During the first time segment, the first drive stage with the smallest current is employed. After subsequent delays, additional drive stages are employed and the load current is sequentially increased. Each drive stage employs a specifically sized feedback device which, depending upon its dimensions will provide either parasitic capacitance to slow transitions or positive feedback to speed up transitions. The first stages are sized to incorporate parasitic capacitance, resulting in little change in the settling time of small capacitance loads over prior art output buffers. Latter stages use positive feedback to quicken the transition time which dramatically improves the settling time for larger load capacitances over prior art output buffers.

Claims28

Dependent claims

A method of controlling the slew rate on the output terminal of an output buffer wherein the current delivered to said output terminal is varied during voltage transitions by dividing the output transition into various time and current drive segment in following steps:

sequentially turning on a plurality of n first conducting devices when said voltage transition of said output terminal is from a first voltage level to a second voltage level thereby connecting said output terminal to a first fixed voltage potential, wherein said sequentially turning on said plurality of n first conducting devices is accomplished by turning on of each of said first conducting devices after a delay such that the first of said plurality of first conducting devices has the shortest said delay and subsequent conducting devices have subsequently longer said delays, wherein the time duration of said delay is controlled by a network comprising resistance and capacitance and wherein said capacitance is comprised of the combination of parasitic capacitance of said first conducting device and a first feedback device;
and
sequentially turning on a plurality of m second conducting devices when said voltage transition of said output terminal is from said second voltage level to said first voltage level thereby connecting said output terminal to a second fixed voltage potential wherein said second fixed voltage potential is less than said first fixed potential.

A device for controlling the slew rate on the output terminal of an output buffer wherein the rising transition of the voltage on said output terminal is achieved by sequentially activating a plurality of n distinct pull-up current driver stages each comprised of:

a pull-up signal input terminal;
a pull-up device which when activated will electrically connect said output terminal to a first fixed voltage potential;
a pull-up delay circuit which, when an activating signal is presented to said pull-up signal input terminal, will activate said pull-up device after a pull-up time delay;
a pull-up feedback device which when activated will feedback a portion of the signal on said output terminal to the input of said pull-up device;
a pull-up enabling device which when activated with an enable signal will activate said pull-up feedback device;
and wherein the falling transition of said voltage on said output terminal is achieved by
sequentially activating a plurality of m distinct pull-down current driver stages each comprised of:
a pull-down signal input terminal;
a pull-down device which when activated will electrically connect said output terminal to a second fixed voltage potential;
a pull-down delay circuit which, when an activating signal is presented to said pull-down signal input terminal, will activate said pull-down device after a pull-down time delay;
a pull-down feedback device which when activated will feedback a portion of said signal on said output terminal to the input of said pull-down device;
and
a pull-down enabling device which when activated with an enable signal will activate said pull-down feedback device.

10 more elements

a pull-up signal input terminal;
a PMOS transistor which when activated will electrically connect said output terminal to a first fixed voltage potential;
a pull-up delay circuit which, when an activating signal is presented to said pull-up signal input terminal, will activate said PMOS transitor after a pull-up time delay;
a pull-up feedback device which when activated will feedback a portion of the signal on said output terminal to the gate of said PMOS transitor;
and
a pull-up enabling device which when activated with an enable signal will activate said pull-up feedback device;
wherein the falling transition of said voltage on said output terminal is achieved by
sequentially activating a plurality of m distinct pull-down current driver stages each comprised of:
a pull-down signal input terminal;
an NMOS transistor which when activated will electrically connect said output terminal to a second fixed voltage potential;
a pull-down delay circuit which, when an activating signal is presented to said pull-down signal input terminal, will activate said NMOS transistor after a pull-down time delay;
a pull-down feedback device which when activated will feedback a portion of said signal on said output terminal to the gate of said NMOS transistor;
and
a pull-down enabling device which when activated with an enable signal will activate said pull-down feedback device.

11 more elements

Dependencies are inferred from the claim text.