Generating multi-phase clock signals using hierarchical delays
AssigneeMicron Technology, Inc.
InventorSeong-hoon Lee
Life of this patent
Estimating the term…
Abstract
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.
Claims23
A circuit for receiving a reference clock signal and outputting clock signals having different phases corresponding to said reference clock signal, said circuit comprising:
- a plurality of serially-coupled delay units comprising a first delay unit operative to receive said reference clock signal, said plurality of serially-coupled delay units operative to output clock signals phase-shifted relative to said reference clock signal, at least one said delay unit of said plurality of serially-coupled delay units providing at least three stages of increasingly finer variable phase adjustment controllable by digital signals;
- a phase detector operative to output a signal indicating a phase difference between said reference clock signal and a clock signal output by said plurality of serially-coupled delay units;
- and
- logic circuitry operative to output digital signals to control phase shifts performed by said plurality of serially-coupled delay units based on said output of said phase detector.
A circuit for receiving a reference clock signal and outputting clock signals having different phases corresponding to said reference clock signal, said circuit comprising:
- a plurality of serially-coupled delay units comprising a first delay unit operative to receive said reference clock signal, said plurality of serially-coupled delay units operative to output clock signals phase-shifted relative to said reference clock signal, each said delay unit of said plurality of serially-coupled delay units providing at least two stages of digitally-controlled variable phase adjustment, wherein a delay unit of said plurality of serially-coupled delay units comprises:
- two parallel delay lines each comprising an input coupled to an input of said delay unit, each said delay line operative to output a signal having a phase;
- two parallel phase mixers each operative to receive said output signals from said two parallel delay lines, said two phase mixers each operative to output a signal having a phase between said phases of said delay line output signals;
- and
- a third phase mixer operative to receive said output signals from said two parallel phase mixers, said third phase mixer operative to output a third signal having a third phase;
- a phase detector operative to output a signal indicating a phase difference between said reference clock signal and a clock signal output by said plurality of serially-coupled delay units;
- and
- logic circuitry operative to digitally control phase shifts of said plurality of said serially-coupled delay units based on said output of said phase detector.
A method of outputting clock signals having different phases corresponding to a reference clock signal, said method comprising:
- receiving said reference clock signal;
- generating a plurality of clock signals each phase-shifted differently relative to said reference clock signal, at least one of said generated phase-shifted clock signals generated via at least three stages of increasingly finer phase adjustment;
- measuring phase difference between said reference clock signal and a clock signal of said plurality of clock signals;
- and
- adjusting if necessary phase shifts of said plurality of clock signals based on said measuring.
A method of outputting clock signals having different phases corresponding to a reference clock signal, said method comprising:
- receiving said reference clock signal;
- generating a plurality of clock signals each phase-shifted differently relative to said reference clock signal;
- measuring phase difference between said reference clock signal and a clock signal of said plurality of clock signals;
- adjusting coarsely phase shifts of said plurality of clock signals in response to a measured phase shift;
- adjusting finely said coarsely adjusted phase shifts of said plurality of clock signals in response to a measured phase shift;
- and
- adjusting more finely said finely adjusted phase shifts of said plurality of clock signals in response to a measured phase shift.
Apparatus for outputting multi-phase clock signals corresponding to a reference clock signal, said circuit comprising:
- means for receiving said reference clock signal;
- means for outputting a plurality of clock signals phase-shifted relative to said reference clock signal, said means for outputting comprising means for providing at least three stages of increasingly finer phase adjustment for at least one of said plurality of clock signals;
- means for measuring phase difference between said reference clock signal and a clock signal of said plurality of clock signals;
- and
- means for adjusting phase shifts of said plurality of clock signals based on measurements of said phase difference.
A computer system comprising:
- a processor;
- a memory controller coupled to said processor;
- a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller;
- and
- circuitry for synchronizing with an external clock signal data output by said DRAM chips, said circuitry comprising:
- circuitry for outputting a plurality of clock signals phase-shifted relative to said external clock signal, said circuitry for outputting comprising circuitry for providing at least three stages of increasingly finer phase adjustment for at least one of said plurality of clock signals;
- circuitry for measuring phase difference between said external clock signal and a clock signal of said plurality of clock signals;
- and
- circuitry for adjusting phase shifts of said plurality of clock signals based on measured phase differences.
Dependencies are inferred from the claim text.