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US 7,009,433 B2Granted
Digitally controlled delay cells
AssigneeLattice Semiconductor Corporation
InventorsFulong Zhang, William B. Andrews, Phillip Johnson, Hal Scholz, Zheng (Jeff) Chen, John Schadt
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Abstract
Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
Claims18
A programmable logic device comprising:
- a master delay-locked loop adapted to receive a reference clock signal and provide a digital control signal, wherein the master delay-locked loop comprises;
- a series of delay cells adapted to receive the reference clock signal and provide delayed versions of the reference clock signal;
- a first multiplexer adapted to select either the reference clock signal or one of the delayed versions of the reference clock signal and provide a first output signal;
- a second multiplexer adapted to select either the reference clock signal or the first output signal and provide a clock output signal from the master delay-locked loop;
- a third multiplexer adapted to select either the reference clock signal or the first output signal and provide a second output signal;
- a fourth multiplexer adapted to select either the reference clock signal or a feedback signal received by the master delay-locked loop and provide a third output signal;
- and
- a control logic circuit adapted to receive the second output signal and the third output signal and generate the digital control signal;
- a plurality of signal paths;
- and
- a plurality of slave delay cells disposed respectively within the plurality of signal paths and adapted to receive the digital control signal and provide a signal delay based on the digital control signal.
8 more elements
A delay cell architecture comprising:
- a master delay cell adapted to receive a reference clock signal and a feedback signal and provide a clock signal and digital control signals, wherein the waster delay cell has means for generating a plurality of delayed versions of the reference clock signal and means for determining a phase between the reference clock signal or one of the plurality of delayed versions of the reference clock signal and the feedback signal or the reference clock signal to determine one or more values for the digital control signals;
- a plurality of slave delay cells disposed on a plurality of corresponding signal paths and adapted to receive the digital control signals, wherein each of the slave delay cells has means for receiving an input signal and selectively applying a delayed output signal based on one of the digital control signals;
- a second master delay cell;
- and
- a memory adapted to provide a static memory digital control signal, wherein the plurality of slave delay cells is further adapted to receive the digital control signals from the second master delay cell and the memory digital control signal, wherein the delayed output signal is based on the memory digital control signal or the digital control signal from master delay cell or second master delay cell.
2 more elements
A method of inserting a delay into a plurality of signal paths of a programmable logic device, the method comprising:
- receiving a reference clock signal;
- generating delayed versions of the reference clock signal;
- receiving a feedback clock signal;
- selecting between the reference clock signal and one of the delayed versions of the reference clock signal to provide a first signal;
- selecting between the reference clock signal and the feedback clock signal to provide a second signal;
- determining a phase difference between the first signal and the second signal;
- and
- providing one or more control signals based on the determined phase difference to delay cells within the plurality of signal paths.
5 more elements
A master delay-locked loop circuit within a programmable logic device, the circuit comprising:
- a series of delay cells adapted to receive a reference clock signal and provide delayed versions of the reference clock signal;
- a first multiplexer adapted to select either the reference clock signal or one of the delayed versions of the reference clock signal and provide a first output signal;
- a second multiplexer adapted to select either the reference clock signal or the first output signal and provide a clock output signal from the master delay-locked loop circuit;
- a third multiplexer adapted to select either the reference clock signal or the first output signal and provide a second output signal;
- a fourth multiplexer adapted to select either the reference clock signal or a feedback signal received by the master delay-locked loop circuit and provide a third output signal;
- and
- a control logic circuit adapted to receive the second output signal and the third output signal and generate a digital control signal.
4 more elements
Dependencies are inferred from the claim text.