Interpolator linearity testing system
AssigneeIntel Corporation
InventorsAdarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla, Arnaud Forestier
Life of this patent
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Abstract
According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.
Claims20
A method comprising:
- interpolating a clock signal;
- receiving the interpolated clock signal having a first frequency;
- periodically sampling the interpolated clock signal based on a reference clock signal to generate a first plurality of periodically-sampled values, the reference clock signal having substantially the first frequency;
- setting a phase of the interpolated clock signal to a phase degree at which a second plurality of periodically-sampled values includes more than one value;
- and
- incrementally changing the phase of the interpolated clock signal until a third plurality of periodically-sampled values includes only one value.
An apparatus comprising:
- an interpolator to generate an interpolated clock signal;
- a reference clock generator to generate a reference clock signal;
- a sampler to input the interpolated clock signal, input the reference clock signal, and periodically sample the interpolated clock signal based on the reference clock signal to generate a first plurality of periodically-sampled values;
- and
- a device coupled to the interpolator and to receive a first plurality of periodically-sampled values, the device to incrementally change a phase of the interpolated clock signal, and to determine whether a second plurality of periodically-sampled values includes only one value or whether the second plurality of periodically-sampled values includes more than one value.
A system comprising:
- a microprocessor comprising:
- an interpolator to generate an interpolated clock signal;
- a reference clock generator to generate a reference clock signal;
- a sampler to periodically sample the interpolated clock signal based on the reference clock signal to generate a first plurality of periodically-sampled values;
- and
- a device to incrementally change a phase of the interpolated clock signal, and to determine whether a second plurality of periodically-sampled values includes only one value or whether the second plurality of periodically-sampled values includes more than one value;
- and
- a fully-buffered dual in-line memory module coupled to the microprocessor.
Dependencies are inferred from the claim text.