High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines

A method, comprising the steps of:

• obtaining an oscillating voltage reference and an oscillating voltage reference complement, the oscillating reference complement being a complement of the oscillating reference;
• receiving the incoming signal;
• comparing by a first comparator the oscillating reference against the incoming signal at a current sampling time to generate a first result;
• comparing by a second comparator the oscillating reference complement against the incoming signal at the current sampling time to generate a second result;
• using a control signal based on the previous logical state of the incoming signal to control whether the first result or the second result passes as an output signal, the output signal defining the current logical state of the incoming signal and acting as the previous logical state of the incoming signal at the next sampling time.

A receiver comprising:

• a first comparator for comparing an oscillating voltage reference and a new signal at a current sampling time;
• a second comparator for comparing a complement of the oscillating voltage reference and the new signal at the current sampling time;
• an output terminal coupled to one of the first and second comparators;
• circuitry for maintaining the comparator that is coupled to the output terminal when the new signal transitions relative to the previous logical state of the incoming signal as determined at the previous sampling time;
• and
• circuitry for coupling to the output terminal one of the first and second comparators that is not coupled to the output terminal and de-coupling from the output terminal one of the first and second comparators that is coupled to the output terminal when the new signal does not transition relative to the previous logical state of the incoming signal as determined at the previous sampling time.