Single supply level shifter

A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal, the level shifter comprising:

• a first NMOS transistor having a source connected to the input signal, a bulk connected to a reference voltage, and a drain connected to an output node;
• a first PMOS transistor having a source connected to the input signal, a drain connected to a gate of the first NMOS transistor at a control node, and a bulk connected to a high power supply voltage source;
• a capacitor having a first terminal connected to the high power supply voltage source and a second terminal connected to the gate of the first NMOS transistor and the drain of the first PMOS transistor at the control node;
• a second NMOS transistor having a source connected to the reference voltage, a drain connected to an output node, and a gate connected to a gate of the first PMOS transistor at an inverted output node;
• a third NMOS transistor having a gate connected to the input signal, a source connected to the reference voltage, and a drain connected to the gate of the second NMOS transistor;
• a second PMOS transistor having a drain connected to the drain of the second NMOS transistor at the output node, and a source connected to the high power supply voltage source;
• and
• a third PMOS transistor having a source connected to the high power supply voltage source, a drain connected to a gate of the second PMOS transistor and the drain of the third NMOS transistor, and a gate connected to the output node.

A level shifter that shifts a low supply voltage input signal to a higher supply voltage output signal, the level shifter comprising:

• a first PMOS transistor having a source and a bulk connected to a high power supply voltage source, and a gate connected to its drain;
• a second PMOS transistor having a source and a bulk connected to the drain of the first PMOS transistor, and a gate connected to its drain;
• a third PMOS transistor having a source and a bulk connected to the drain of the second PMOS transistor, and a gate connected to its drain;
• a fourth PMOS transistor having a source and a bulk connected to the drain of the third PMOS transistor, and a gate connected to the input signal;
• a first NMOS transistor having a source and a bulk connected to a reference voltage, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the input signal and the gate of the fourth PMOS transistor;
• a fifth PMOS transistor having a gate connected to the reference voltage, a source connected to the gate of the third PMOS transistor, a bulk connected to its source, and a drain connected to its source;
• a second NMOS transistor having a source and a bulk connected to the reference voltage, and a gate connected to the input signal;
• a third NMOS transistor having a source and a bulk connected to the reference voltage, and a gate connected to the drain of the fourth PMOS transistor;
• a sixth PMOS transistor having a source and a bulk connected to the high power supply voltage source, and a drain connected to the drain of the second NMOS transistor;
• a seventh PMOS transistor having a source and a bulk connected to the high power supply voltage source, a drain connected to the drain of the third NMOS transistor and a gate of the sixth PMOS transistor at an output node, and a gate connected to the drain of the sixth PMOS transistor;
• and
• an eighth PMOS transistor having a source and a bulk connected to the high power supply voltage, a drain connected to the gate of the third NMOS transistor, and a gate connected to the drain of the third NMOS transistor, wherein the higher power supply voltage signal is provided at the output node.