Programmable I/O interfaces for FPGAs and other PLDs

A programmable logic device (PLD), comprising:

• a logic core connected to an I/O interface, the I/O interface comprising one or more programmable I/O buffers (PIBs), wherein at least one PIB comprises:
• multiplexing circuitry programmable to multiplex two or more outgoing single data rate (SDR) data signals from the logic core of the PLD into at least one higher-rate SDR data signal;
• and
• double data rate (DDR) circuitry coupled to the multiplexing circuitry and programmable to convert the at least one higher-rate SDR data signal into an outgoing DDR data signal.

A programmable logic device (PLD), comprising:

• a logic core connected to an I/O interface, the I/O interface comprising one or more programmable I/O buffers (PIBs), wherein at least one PIB comprises:
• multiplexing circuitry programmable to multiplex four or more lower-rate single data rate (SDR) data signals into two higher-rate SDR data signals;
• demultiplexing circuitry programmable to demultiplex two higher-rate SDR data signals into four or more lower-rate SDR data signals;
• and
• double data rate (DDR) circuitry coupled to the demultiplexing circuitry and programmable to convert an incoming DDR data signal into two higher-rate single data rate (SDR) data signals for the demultiplexing circuitry and further coupled to the multiplexing circuitry and programmable to convert two higher-rate SDR data signals from the multiplexing circuitry into an outgoing DDR data signal.