Field programmable gate array core cell with efficient logic packing
AssigneeAgate Logic, Inc.
InventorsDaniel J. Pugh, Andrew W. Fox, Dale Wong
Life of this patent
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Abstract
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
Claims13
A method of mapping a given Boolean network into an FPGA, said FPGA having a plurality of core cells, each core cell having a predetermined number of input terminals and one or more output terminals;
- one or more LUTs, each LUT having a plurality of input terminals, each input terminal of each LUT connected to one of said core cell input terminals, and an output terminal;
- a selectable logic gate having a plurality of input terminals, each input terminal connected to one of said LUT output terminals or to any remaining core cell input terminal not connected to an LUT input terminal, and an output terminal;
- and circuitry selectably connecting said output terminals of said LUTs and said selectable logic gate to said core cell output terminals;
- whereby said core cell is programmed by setting configuration bits in said one or more LUTs, selecting said logic gate and selectably connecting said output terminals of said one or more LUTs and of said selectable logic gate to said core cell output terminals, said method comprising
- partitioning said logic network into a plurality of cuts, each partitioning cut having no more than said predetermined number of core cell input terminals and mapping into logic of said partitioned cut;
- generating a network graph of each partitioning cut;
- partitioning input terminals of each partitioning cut into input sets corresponding to input terminals of said LUTs of said core cell in different combinations;
- generating a network graph for each input partitioning cut for all input combinations;
- determining equivalence between said network graphs of each partitioning cut, and logic combinations of said partitioning cuts for different logic;
- and
- finding an equivalence match for a mapping for logic of each partitioning cut into a logic cell core configured for matching input combination and selected logic gate;
- whereby said Boolean network is mapped into said FPGA with said matched configured core cells.
An integrated circuit having an FPGA core having a Boolean network mapped thereinto, said FPGA having a plurality of core cells, each core cell having a predetermined number of input terminals and a plurality of output terminals;
- one or more LUTs, each LUT having a plurality of input terminals, each input terminal of each LUT connected to one of said core cell input terminals, and an output terminal;
- a selectable logic gate having a plurality of input terminals, each input terminal connected to one of said LUT output terminals or to any remaining core cell input terminal not connected to an LUT input terminal, and an output terminal;
- and circuitry selectably connecting said output terminals of said LUTs and said selectable logic gate to said core cell output terminals;
- whereby said core cell is programmed by setting configuration bits in said one or more LUTs, selecting said logic gate and selectably connecting said output terminals of said one or more LUTs and of said selectable logic gate to said core cell output terminals, said FPGA core cells configured by:
- partitioning said logic network into a plurality of cuts, each partitioning cut having no more than said predetermined number of core cell input terminals and mapping into logic of said partitioned cut;
- generating a network graph of each partitioning cut;
- partitioning input terminals of each partitioning cut into input sets corresponding to input terminals of said LUTs of said core cell in different combinations;
- generating a network graph for each input partitioning cut for all input combinations;
- determining equivalence between said network graphs of each partitioning cut, and logic combinations of said partitioning cuts for different logic;
- finding an equivalence match for a mapping for logic of each partitioning cut into a logic cell core configured for matching input combination and selected logic gate;
- and
- configuring said core cells for said equivalence matches whereby said Boolean network is mapped into said FPGA.
Dependencies are inferred from the claim text.