US 7,009,419 B2 · Method and apparatus for selecting an encryption integrated circuit operating mode

Abstract

A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Claims7

Dependent claims

An apparatus for processing or storing secure data comprising:

a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data;
and
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period, the test mode entry circuit being coupled to the secure port, the test mode entry circuit causing entry of the apparatus into a work mode when secure data is applied to the secure port.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for selecting an encryption integrated circuit operating mode

Life of this patent

Method and apparatus for selecting an encryption integrated circuit operating mode

Life of this patent

Abstract

Claims7