Delay lock circuit having self-calibrating loop
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
Estimating the term…
Abstract
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to generate an internal signal. The feedback path includes a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal. The delay lock circuit further includes a monitoring unit for monitoring the measurement. Based on the monitoring, the monitoring unit enables the calibrating unit to conditionally adjust the width of the pulse.
Claims26
A circuit comprising:
- a measuring path for receiving a reference signal to sample a pulse to obtain a measured delay;
- a forward path connected to the measuring path for delaying the reference signal based on the measured delay to generate an internal signal;
- and
- a feedback path connected to the measuring path and the forward path, the feedback path including a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal, wherein the calibrating unit is configured to conditionally adjust a pulse width of the pulse.
A memory device comprising:
- a memory array for storing data;
- an output data path for outputting the data;
- and
- a delay lock circuit connected to the data path for providing an internal signal to control a transfer of data at the output data path, the delay lock circuit including:
- a measuring path for receiving a reference signal to sample a pulse to obtain a measured delay;
- a forward path connected to the measuring path for delaying the reference signal based on the measured delay to generate the internal signal;
- and
- a feedback path connected to the measuring path and the forward path, the feedback path including a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal, wherein the calibrating unit is configured to conditionally adjust a pulse width of the pulse.
A system comprising:
- a processor;
- and
- a memory device connected to the processor, the memory device including:
- a memory array for storing data;
- an output data path for outputting the data;
- and
- a delay lock circuit connected to the data path for providing an internal signal to control a transfer of data at the output data path, the delay lock circuit including:
- a measuring path for receiving a reference signal to sample a pulse to obtain a measured delay;
- a forward path connected to the measuring path for delaying the reference signal based on the measured delay to generate the internal signal;
- and
- a feedback path connected to the measuring path and the forward path, the feedback path including a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal, wherein the calibrating unit is configured to conditionally adjust a pulse width of the pulse.
Dependencies are inferred from the claim text.