Micromachine package and method for manufacturing the same
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorSu Tao
Life of this patent
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AssigneeAdvanced Semiconductor Engineering, Inc.
InventorSu Tao
Estimating the term…
A micromachine package includes a first chip, a second chip, a spacer ring, a plurality of bumps, a plurality of leads, and an encapsulant. The first chip has at least one moveable structure. The second chip has at least one electrode for cooperating with the moveable structure of the first chip, and a plurality of pads disposed on one side of the second chip. The spacer ring is disposed between the first chip and the opposite second chip and surrounds the moveable structure. The bumps are disposed on the pads. The lead has a first surface, which is connected to the bumps, and an opposite second surface. The encapsulant encapsulates the first chip, the second chip, the spacer ring, the bumps, and the first surfaces of the leads, and the second surfaces of the leads are exposed out of the encapsulant.
A micromachine package comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Packages or encapsulation: other packages not provided for in groups B81B7/0035 - B81B7/0074
By means of one or more reflecting elements: the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
Packaging MEMS: bonding a wafer on the substrate, i.e. where the cap consists of another wafer
Configurations of stacked chips: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks…
Term ended 19 Apr 2024 (estimated)
This application claims the priority benefit of Taiwan patent application Ser. No. 092120272, filed on Jul. 24, 2003, and the full disclosure thereof is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor package and a manufacturing method therefor, and more particularly, to a micromachine package with a hermetic cavity and a manufacturing method therefor.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a micromachine package in prior art.
FIG. 2 is a schematic cross-sectional view of another micromachine package in prior art.
Now referring to FIG. 4, it depicts a micromachine package 100 according to an embodiment of the present invention. The micromachine package 100 comprises a micromachine chip 120 having moveable structures 122, such as micromachines or micromirrors, and a semiconductor chip 110, such as complimentary metal-oxide semiconductor (CMOS), having electrodes 112 corresponding to the moveable structures 122. The semiconductor chip 110 is fixed on the micromachine chip 120 by means of an adhesive or a spacer ring 124, and is uniformly spaced apart from the micromachine chip 120. A cavity 116 is formed between the semiconductor chip 110 and the micromachine chip 120 so that the moveable structures 122 cooperate with the electrodes 112 and freely move within the cavity 116.
It should be noted that the moveable structures 122 and electrodes 112 are disposed on the chip 120 and the chip 110, respectively.
The micromachine chip 120 is attached on a die pad 142 of a lead frame 140 by means of an adhesive 126. The adhesive 126 can be a conductive paste for electrically connecting the micromachine chip 120 to the die pad 142. The semiconductor package 100 is provided with a plurality of solder pads 118 disposed on the two adjacent sides thereof, which will be described hereinafter, and electrically connected to the electrodes 112. The solder pad 118 is connected to a bump 114, such as a gold bump or a solder bump. The bumps 114 are individually disposed on a plurality of leads 144 of the lead frame 140. An encapsulant 130 encapsulates the micromachine chip 120, the semiconductor chip 110, the bumps 114, and the lead frame 140. The leads 144 and the die pad 142 of the lead frame 140 respectively have lower surfaces 148 and a lower surface 146 which are exposed out of and are flush with the encapsulant 130 for being connected to an external print circuit board (not shown). Therefore, the leads 144 are referred to Quad Flat No-lead (QFN)-type leads. The lower surface 146 of the die pad 142 can also be used for grounding or dissipating heat.