Low profile stacked multi-chip package and method of forming same
AssigneeIntel Corporation
InventorRodolfo L. Gacusan
Life of this patent
Estimating the term…
Abstract
A stacked multi-chip package includes first chip with conductive pads on both front and back sides. The front side may include a polymer layer with interconnect. A first polymer layer formed on the backside of the first chip has a cutout to receive a second chip. The first and second chip may be joined as a flip chip. A second polymer layer formed on the first polymer layer has a cutout to receive a third chip. A third polymer layer formed on the second polymer layer contains interconnect to interconnect the first, second and third chips, including the backside of the first chip. Conductive bumps on the front side of the first chip and on the polymer layers provide external I/O connection.
Claims22
An integrated circuit package, comprising:
- a first chip having a first side and a second side, the first and second sides having a first plurality of conductive pads formed thereon, at least one conductive pad on the first side being electrically connected to a conductive pad on the second side, the first side containing active circuitry of the first chip;
- a first layer formed directly on the second side and having a first cutout, wherein the first layer comprises a polymer material;
- a second chip disposed in the first cutout;
- a dielectric second layer formed directly on the first layer and the second chip and having a second cutout;
- a third chip disposed in the second cutout;
- a third dielectric layer formed directly on the second layer and the third chip;
- and
- an interconnect formed in the one or more of the first, second or third layers to electrically connect at least one conductive pad of the first plurality of conductive pads to one or more of the second and third chips.
An integrated circuit package, comprising:
- a first chip having a first side and a second side, the first and second sides having a first plurality of conductive pads formed thereon, at least one conductive pad on the first side being electrically connected to a conductive pad on the second side, the first side containing active circuitry of the first chip;
- a first layer formed directly on the second side and having a first hole, wherein the first layer comprises a polymer material;
- a second chip disposed in the first hole;
- a second dielectric layer formed directly on the second chip and having a second hole;
- a third chip disposed in the second hole;
- a third dielectric layer formed directly on the third chip;
- and
- an interconnect formed in the one or more of the first, second or third layers to electrically connect at least one conductive pad of the first plurality of conductive pads to one or more of the second and third chips.
An integrated circuit package, comprising:
- a first chip having a first side and a second side, the first and second sides having a first plurality of conductive pads formed thereon, at least one conductive pad on the first side being electrically connected to a conductive pad on the second side, the first side containing active circuitry of the first chip;
- a first layer formed directly on the second side and having a first hole, wherein the first layer comprises a polymer material;
- a second chip disposed in the first hole, wherein the second chip is in contact with the second side;
- a second dielectric layer formed directly on the second chip and having a second hole;
- a third chip disposed in the second hole, wherein the third chip is in contact with the second chip;
- a third dielectric layer formed directly on the third chip;
- and
- an interconnect formed in the one or more of the first, second or third layers to electrically connect at least one conductive pad of the first plurality of conductive pads to one or more of the second and third chips.
Dependencies are inferred from the claim text.