US 7,009,296 B1 · Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die

Abstract

Semiconductor packages are disclosed. One semiconductor package includes a semiconductor die with an active surface, an opposite inactive surface, and four peripheral side surfaces. A substrate of the semiconductor package is coupled to one side surface of the semiconductor die. Bond pads of the active surface are coupled to a substrate first surface that is coplanar with the active surface. External interconnects, e.g., solder balls, are formed on a second substrate surface that is perpendicular to the active surface. An insulating layer, e.g., an encapsulant, together covers the active surface and the substrate first surface. An alternative semiconductor package includes two substrates, each attached to a respective one of two opposed side surfaces of the semiconductor die. The remaining two side surfaces of the semiconductor die are exposed. The external interconnects are formed on a third substrate surface that is coplanar with the inactive surface of the semiconductor die.

Claims20

Dependent claims

A semiconductor package comprising:

a semiconductor die comprising an active surface with bond pads thereon, an opposite inactive surface, and four peripheral side surfaces extending between the active and inactive surfaces;
a substrate comprising a first surface, a second surface opposite and parallel to the first surface, a third surface extending between the first and second surfaces, and conductive circuit patterns at the second and third surfaces,
wherein the first surface of the substrate is coupled to only a first one of the four peripheral side surfaces of the semiconductor die, the third surface of the substrate is coplanar with the active surface of the semiconductor die, and the bond pads of the semiconductor die are electrically coupled to the conductive circuit patterns of the third surface of the substrate;
and
external interconnects electrically coupled to the circuit patterns of the second surface of the substrate, whereby at least some of the external interconnects are electrically coupled to the semiconductor die.

2 more elements

A semiconductor package comprising:

a semiconductor die comprising an active surface with bond pads thereon, an opposite inactive surface, and four peripheral side surfaces extending between the active and inactive surfaces;
first and second substrates each comprising a first surface, a second surface opposite and parallel to the first surface, a third surface extending between the first and second surfaces, and conductive circuit patterns at the first and second surfaces,
wherein the third surface of the first substrate is coupled only to a first of the four side surfaces of the semiconductor die, the third surface of the second substrate is coupled only to a second of the four side surfaces of the semiconductor die, the second side surface being opposite to the first side surface, and the first surface of each of the two substrates is coplanar with the active surface of the semiconductor die,
wherein the circuit patterns of the first surface of the first and second substrates are electrically coupled to the circuit patterns of the second surface of the respective substrate, and
wherein some of the bond pads of the semiconductor die are electrically coupled to the circuit patterns of the first surface of the first substrate, and some of the bond pads of the semiconductor die are electrically coupled to the circuit patterns of the first surface of the second substrate;
and
external interconnects electrically coupled to the circuit patterns of the second surface of the first and second substrates, whereby the external interconnects of the first and second substrates are electrically coupled to the semiconductor die.

4 more elements

A semiconductor package comprising:

a semiconductor die comprising an active surface with bond pads thereon, an opposite inactive surface, and four peripheral side surfaces extending between the active and inactive surfaces;
first and second substrates each comprising a first surface, a second surface opposite and parallel to the first surface, a third surface extending between the first and second surfaces, and conductive circuit patterns at the first and second surfaces,
wherein the third surface of the first substrate is coupled only to a first of the four side surfaces of the semiconductor die, the third surface of the second substrate is coupled only to a second of the four side surfaces of the semiconductor die, with the second side surface being opposite and parallel to the first side surface of the semiconductor die, and the first surface of the first and second substrates is coplanar with the active surface of the semiconductor die,
wherein at least some of the circuit patterns of the first surface of the first and second substrates are electrically coupled through the respective substrate to at least some of the circuit patterns of the second surface of the substrate, and
wherein some of the bond pads of the semiconductor die are electrically coupled by bond wires to the circuit patterns of the first surface of the first substrate, and some of the bond pads of the semiconductor die are electrically coupled by bond wires to the circuit patterns of the first surface of the second substrate;
solder balls electrically coupled to the circuit patterns of the second surface of the first and second substrates, whereby the solder balls of the first and second substrates are electrically coupled to the semiconductor die;
and
a layer of an encapsulant overlying the active surface of the semiconductor die, the bond wires, and the first surface of the first and second substrates,
wherein the inactive surface of the semiconductor die and the remaining two of the four side surfaces of the semiconductor die are exposed.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die

Life of this patent

Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die

Life of this patent

Abstract

Claims20