Package type semiconductor device

A package type semiconductor device comprising:

• a semiconductor chip having a semiconductor part;
• a main electrode disposed on a principal surface of the chip for electrically connecting to a first region of the semiconductor part;
• a control wiring layer disposed on the principal surface of the chip for electrically connecting to a second region of the semiconductor part and for controlling an electric potential of the second region of the semiconductor part;
• a stress relaxation wiring layer disposed on the principal surface of the chip and electrically isolated from the control wiring layer;
• a first metallic layer disposed on the principal surface of the chip;
• a second metallic layer disposed on a surface of the stress relaxation wiring layer;
• a protection film for covering the main electrode, the control wiring layer and the stress relaxation wiring layer;
• and
• a metal block for covering at least a part of the main electrode and the control wiring layer for electrically connecting to the main electrode through the first metallic layer,
• wherein the chip, the main electrode, the control wiring layer, the stress relaxation wiring layer, and the metal block are packaged, and
• wherein the stress relaxation wiring layer is disposed outside of the main electrode and connect to the metal block.