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US 7,009,278 B2Granted
3d rram
AssigneeSharp Laboratories of America, Inc.
InventorSheng Teng Hsu
Life of this patent
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Abstract
A memory array layer for use in a 3D RRAM is formed, with peripheral circuitry, on a silicon substrate; layers of silicon oxide, bottom electrode material, silicon oxide, resistor material, silicon oxide, silicon nitride, silicon oxide, top electrode and covering oxide are deposited and formed. Multiple memory array layers may be formed on top of one another. The RRAM of the invention may be programmed in a single step or a two step programming process.
Claims3
A memoly array layer for use in a 3D RRAM comprising, on a silicon substrate having peripheral circuitry thereon:
- a first layer of silicon oxide, deposited and planarized;
- a bottom electrode formed of a material taken from the group of materials consisting of Pt, PtRhOx, PtIrOx and TiN/Pt;
- a second oxide layer having a thickness of at least 1.5× that of the thickness of the bottom electrode, deposited and planarized to a level where at the bottom electrode is exposed;
- a layer of memory resistor material;
- a layer of Si3N4;
- a third oxide layer having a thickness of about 1.5× of that of the memory resistor material;
- CMPd to expose the memory resistor surface;
- a top electrode formed of a material taken from the group of materials consisting of Pt, PtRhOx, PtIrOx and TiN/Pt;
- and
- a covering oxide layer.
7 more elements
Dependencies are inferred from the claim text.