US 7,009,259 B2 · Semiconductor device and method of fabricating same

Abstract

A semiconductor device (100) according to the present invention comprises a vertical PNP bipolar transistor (20), an NMOS transistor (50) and a PMOS transistor (60) that are of high dielectric strength, and a P-type semiconductor substrate 1, as shown in FIG. 2. A substrate isolation layer (21) of the PNP bipolar transistor (20), a drain buried layer (51) of the NMOS transistor (50), and a back gate buried layer (61) of the PMOS transistor (60) are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (1). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

A semiconductor device comprising a bipolar transistor having an emitter and a collector of one conductive type and a base of an opposite conductive type, a field effect transistor of the opposite conductive type, a field effect transistor of the one conductive type, a first semiconductor layer of the one conductive type on which the transistors are formed, a second semiconductor layer of the opposite conductive type, formed on said first semiconductor layer, said bipolar transistor including:

a first impurity diffusion layer of the opposite conductive type for interlayer isolation use, formed between said second semiconductor layer and said first semiconductor layer;
a second impurity diffusion layer of the one conductive type for collector use, formed in said second semiconductor layer region over said first impurity diffusion layer;
a third impurity diffusion layer of the opposite conductive type for base use, formed on one side of said second impurity diffusion layer;
a fourth impurity diffusion layer of the opposite conductive type for base contact use, formed on one side of said third impurity diffusion layer;
a fifth impurity diffusion layer of the one conductive type for emitter use, formed on the other side of said third impurity diffusion layer;
and
a sixth impurity diffusion layer of the one conductive type for collector contact use, formed on the other side of said second impurity diffusion layer,
said field effect transistor of the opposite conductive type including:
a first impurity diffusion layer of the opposite conductive type for drain burying use, formed between said second semiconductor layer and said first semiconductor layer;
a second impurity diffusion layer of the one conductive type for channel use, formed on one side of said second semiconductor layer region over said first impurity diffusion layer for drain burying use;
a third impurity diffusion layer of the opposite conductive type for source use, formed in said second impurity diffusion layer for channel use;
and
a fourth impurity diffusion layer of the opposite conductive type for drain contact use, formed on the other side of said second semiconductor layer region, and said field effect transistor of the one conductive type including:
a first impurity diffusion layer of the opposite conductive type for back gate use, formed between said second semiconductor layer and said first semiconductor layer;
a second impurity diffusion layer of the one conductive type for drain use, formed on one side of said second semiconductor layer region over said first impurity diffusion layer for back gate use;
a third impurity diffusion layer of the one conductive type for source use, formed on the other side of said second semiconductor layer region;
and
a fourth impurity diffusion layer of the one conductive type for drain contact use, formed in said second impurity diffusion layer for drain use,
wherein the first impurity diffusion layer of said bipolar transistor, the first impurity diffusion layer of said field effect transistor of the opposite conductive type, and the first impurity diffusion layer of said field effect transistor of the one conductive type are formed simultaneously by selectively implanting impurities of the opposite conductive type in said first semiconductor layer,
wherein said second impurity diffusion layer of said bipolar transistor is a P-type collector region,
wherein said third impurity diffusion layer of said bipolar transistor is an N-type base region, and
wherein said fourth impurity diffusion layer of said bipolar transistor is an N-type base contact region.

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Semiconductor device and method of fabricating same

Life of this patent

Semiconductor device and method of fabricating same

Life of this patent

Abstract

Claims6