US 7,009,202 B2Granted

Thin film transistor array panel having a means for visual inspection

AssigneeSamsung Electronics Co., Ltd.

InventorsYong-Kyu Jang, Won-Kyu Lee, Jin Jeon

Life of this patent

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Abstract

A plurality of gate lines and a plurality of data lines intersecting the gate lines to define a display area are formed on an insulating substrate including a display area and a surrounding area. On the surrounding area, a gate driving circuit connected to the gate lines and a logic circuit for VI interposed between the gate driving circuit and the gate line and having several first to third NOR gates are formed. A first input terminal of the first NOR gate of the logic circuit for VI is connected to an output terminal of the gate driving circuit, and a second input terminal thereof is connected to a CON1 terminal, and an output terminal thereof is connected to a first input terminal of the second or the third NOR gate. A second input terminal of the second NOR gate is connected to a CON2 terminal and an output terminal thereof is connected to the gate lines in odd number. A second input terminal of the NOR gate is connected to a CON3 terminal and an output terminal thereof is connected to the gate lines in even number.

Claims9

Dependent claims

A thin film transistor panel comprising:

an insulating substrate having a display area and a surrounding area;
a plurality of gate lines formed on the insulating substrate;
a data driving signal line formed on the surrounding area of the insulating substrate;
a data inspection signal line formed on the surrounding area of the insulating substrate;
a gate insulating layer formed on the gate lines, the data driving signal line and the data inspection signal line;
a first semiconductor pattern formed on the gate insulating layer, at least a portion thereof overlapping the data driving signal lines;
first and second ohmic contact layers formed on the first semiconductor pattern, exposing therebetween a portion of the first semiconductor pattern corresponding to the data driving signal line;
a plurality of data lines formed on the gate insulating layer and intersecting the gate lines to define the display area, at least a portion thereof being formed on the second ohmic contact layer;
a first electrode for inspection formed on the gate insulating layer, at least a portion thereof being formed on the first ohmic contact layer;
a passivation layer formed on the data lines and the first electrode for inspection;
and
a first connection portion formed on the passivation layer and connecting the data inspection signal line and the first electrode for inspection.

9 more elements

A thin film transistor panel comprising:

an insulating substrate comprising a display area and a surrounding area;
a plurality of gate lines formed on the insulating substrate;
a plurality of data lines formed on the insulating substrate and intersecting the gate lines to define the display area;
a gate driving circuit formed on the surrounding area and connected to the gate lines;
and
a logic circuit for visual inspection (VI) inserted between the gate driving circuit and the gate lines and having a plurality of first to third NOR gates,
wherein a first input terminal of the first NOR gate of the logic circuit for visual inspection is connected to an output terminal of the gate driving circuit and a second input terminal thereof is connected to a CON1 terminal and an output terminal thereof is connected to a first input terminal of the second or the third NOR gate, and a second input terminal of the second NOR gate is connected to a CON2 terminal and an output terminal thereof is connected to the gate lines in odd number, and a second input terminal of the third NOR gate is connected to a CON3 terminal and an output terminal thereof is connected to the gate lines in even number.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/843,270Filed 11 May 2004 · division
Priority: KR 2001-6261911 Oct 2001
Published: US 2004/0207018 A121 Oct 2004
Granted: 7 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G02F 1/13454
Conductors connecting electrodes to cell terminals: drivers integrated on the active matrix substrate
H10D 30/0316
Characterised by the gate electrodes: of lateral bottom-gate TFTs comprising only a single gate
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks

Family

Application10/161,236Parent of this division · filed 3 Jun 2002
US 2004/0207018 A1Pre-grant publication · published 21 Oct 2004
US 6,774,398 B2Parent of this division
US 2003/0075718 A1Published application
US 7,009,202 B2This patent

From the US filing history. Foreign family members aren’t listed.