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US 7,009,115 B2Granted
Optimization of routing layers and board space requirements for a ball grid array package
AssigneeBroadcom Corporation
InventorsKevin L. Seaman, Vernon M. Wnek
Life of this patent
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Abstract
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array package is described. The ball grid array package includes a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge not fully populated with pads.
Claims18
A ball grid array package comprising:
- a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns, wherein at least one edge of said array is not fully populated with pads;
- wherein a first edge of said array includes a repeating pattern of a first conductive pad, a space, and a second conductive pad, positioned in series;
- and
- wherein a row or column of said array parallel and adjacent to said first edge is substantially fully populated with conductive pads.
1 more element
An integrated circuit package comprising:
- a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns, wherein an edge of said array is not fully populated with pads;
- wherein said edge includes a repeating pattern of a first conductive pad, a space, and a second conductive pad, positioned in series;
- and
- wherein a row or column of said array parallel and adjacent to said edge is substantially fully populated with conductive pads.
1 more element
Dependencies are inferred from the claim text.