Method of forming gate electrode structure of a semiconductor device

A method of forming a gate electrode structure of a semiconductor device, comprising:

• forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined;
• forming a buffer layer on the polysilicon film;
• subsequently doping the polysilicon film by implanting N-type impurities into one portion of the polysilicon film, and implanting P-type impurities into another portion of the polysilicon film;
• subsequently removing the buffer layer;
• subsequently forming an anti-reflection layer on the doped polysilicon film;
• and
• forming gate patterns on the semiconductor substrate by etching the anti-reflection layer, the doped polysilicon film and the gate insulation film.

A method of forming a gate electrode structure of a semiconductor device, comprising:

• forming a gate insulation film on semiconductor substrate where an active region and a field region are defined;
• forming a polysilicon film on the gate insulation film, and doping the polysilicon film in-situ with N-type impurities;
• subsequently forming a buffer layer on the polysilicon film;
• subsequently doping the polysilicon film by selectively implanting P-type impurities into a portion of the polysilicon film;
• subsequently removing the buffer layer;
• forming an anti-reflection layer on the polysilicon film doped with the N-type and P-type impurities;
• and
• forming gate patterns by etching the anti-reflection layer, the doped polysilicon film and the gate insulation film.

A method of forming a gate electrode of a semiconductor device comprising:

• forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined;
• forming a buffer layer on the polysilicon film to prevent the polysilicon film from being damaged;
• subsequently doping a portion of the polysilicon film by selectively implanting N-type impurities into the polysilicon film;
• forming gate patterns by etching the polysilicon film, and the gate insulation film, one of the gate patterns including the portion of the polysilicon film doped with the N-type impurities;
• and
• carrying out a P-type ion implantation process comprising implanting P-type impurities into another one of the gate patterns, that does not include the portion of the polysilicon film doped with the N-type impurities during said selective implanting of the N-type impurities, to form a P-type gate electrode.