Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device that includes a first-type transistor, a second-type transistor, and a third-type transistor, the method comprising:

• forming a first mask layer above a first transistor forming region in which the first-type transistor is formed, a second transistor forming region in which the second-type transistor is formed, and a third transistor forming region in which the third-type transistor is formed of a semiconductor layer;
• subsequently forming a second mask layer above the first mask layer;
• selectively removing portions of the first mask layer and the second mask layer above a first gate insulation layer forming region of the first-type transistor;
• subsequently forming a first insulation layer on the first transistor forming region by a thermal oxidation method with the first mask layer and the second mask layer as a mask;
• removing portions of the second mask layer remaining above the first transistor forming region, the second transistor forming region, and the third transistor forming region;
• removing only the portion of the first mask layer formed above the third transistor forming region;
• subsequently forming a multilayer film above the first transistor forming region, the second transistor forming region, and the third transistor forming region, the multilayer film being formed with at least a silicon oxide layer and a silicon nitride layer;
• subsequently removing portions of the multilayer film formed above the first transistor forming region and the second transistor forming region concurrently;
• subsequently removing only the portion of the first mask layer remaining above the second transistor forming region;
• forming a second gate insulation layer on the second transistor forming region;
• simultaneously forming a gate electrode above each of the first transistor forming region, the second transistor forming region, and the third transistor forming region;
• and
• forming a source-drain region in each of the first transistor forming region, the second transistor forming region, and the third transistor forming region.

A method for manufacturing a semiconductor device that includes a high-breakdown-voltage transistor, a low-voltage-drive transistor, and a MNOS type memory transistor, the method comprising the following steps in the order recited:

• forming a first mask layer above a high-breakdown-voltage transistor forming region in which the high-breakdown-voltage transistor is formed, a low-voltage-drive transistor forming region in which the low-voltage-drive transistor is formed, and a MNOS type memory transistor forming region in which the MNOS type memory transistor is formed of a semiconductor layer;
• forming a second mask layer above the first mask layer;
• selectively removing portions of the first mask layer and the second mask layer above a first gate insulation layer forming region of the high-breakdown-voltage transistor;
• forming a first insulation layer on the high-breakdown-voltage transistor forming region by a thermal oxidation method with the first mask layer and the second mask layer as a mask;
• removing portions of the second mask layer remaining above the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region;
• removing only the portion of the first mask layer formed above the MNOS type memory transistor forming region;
• forming a multilayer film above the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region, the multilayer film being formed with at least a silicon oxide layer and a silicon nitride layer;
• simultaneously removing portions of the multilayer film formed above the high-breakdown-voltage transistor forming region and the low-voltage-drive transistor forming region;
• removing only the portion of the first mask layer remaining above the low-voltage-drive transistor forming region;
• forming a second gate insulation layer on the low-voltage-drive transistor forming region;
• simultaneously forming a gate electrode above each of the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region;
• and
• forming a source-drain region in each of the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region.