Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts

A method for providing bitline contacts in a memory cell array, which comprises:

• disposing a plurality of bitlines in a first direction on a substrate;
• disposing a plurality of wordlines in a second direction crossing the first direction above the bitlines on the substrate;
• disposing memory cells where the bitlines and wordlines cross one another, the memory cells forming a memory cell array;
• covering the bitlines with a first isolating layer;
• covering, with at least one second isolating layer, all portions of the memory cell array between the bitlines not covered by the wordlines;
• removing the first isolating layer from the bitlines by a step in which also a topmost of the at least one second isolating layer is removed from the memory cell array at portions not covered by the wordlines, carrying out the removing step by:
• depositing a photoresist material;
• photolithographically patterning the photoresist material causing the photoresist material to be removed within the memory cell array but remain in a peripheral portion of the array;
• and
• selectively etching each of the second and first isolation layers causing the isolation layer to be completely removed from the bitlines in areas not covered by the word lines;
• and
• providing an electrical conductive material on exposed portions of the bitlines.

A method of fabricating a nitride read only memory chip, which comprises:

• providing a memory cell array with memory cells, bitlines, and wordlines, each of the memory cells having a metal-insulator-semiconductor field effect transistor with the insulator being an oxide-nitride-oxide multi-layer stack for storing at least one injected electron;
• disposing the bitlines in a first direction and the wordlines in a second direction perpendicular to the first direction and above the bitlines;
• disposing the memory cells at points at which the bitlines and the wordlines cross one another and at which the bitlines are covered by an isolating layer;
• providing a peripheral portion having logic components;
• providing an electrical contact between the bitlines and metal lines to be formed in a following step by forming bitline contacts by:
• removing the isolating layer completely from the bitlines at portions not covered by the wordlines with areas between the bitlines remaining unaffected, carrying out the step of removing the isolating layer from the bitlines by:
• depositing a photoresist material;
• patterning the photoresist material using a mask having a stripe pattern;
• and
• selectively etching the isolating layer with respect to the wordlines;
• and
• providing an electrical conductive material on exposed portions of the bitline;
• and
• disposing the metal lines in the first direction above the bitlines.

A method of fabricating a nitride read only memory chip, which comprises:

• providing a memory cell array with memory cells, bitlines, and wordlines, each of the memory cells having a metal-insulator-semiconductor field effect transistor with the insulator being an oxide-nitride-oxide multi-layer stack for storing at least one injected electron;
• disposing the bitlines in a first direction on a substrate and the wordlines in a second direction perpendicular to the first direction and above the bitlines on the substrate;
• disposing the memory cells at points at which the bitlines and the wordlines cross one another and at which the bitlines are covered by a first isolating layer;
• providing a peripheral portion having logic components;
• providing an electrical contact between the bitlines and metal lines to be formed in a following step by forming bitline contacts by:
• covering, with at least one second isolating layer, all portions of the memory cell array between the bitlines not covered by the wordlines;
• removing the first isolating layer from the bitlines by a step in which also a topmost of the at least one second isolating layer is removed from the memory cell array at portions not covered by the wordlines, carrying out the removing step by:
• depositing a photoresist material;
• photolithographically patterning the photoresist material causing the photoresist material to be removed within the memory cell array but remain in a peripheral portion of the array;
• and
• selectively etching each of the second and first isolation layers causing the isolation layer to be completely removed from the bitlines in areas not covered by the word lines;
• and
• providing an electrical conductive material on exposed portions of the bitlines;
• and
• disposing the metal lines in the first direction above the bitlines.