Semiconductor device having electrically erasable programmable read-only memory (EEPROM) and mask-ROM and method of fabricating the same

A method of fabricating a semiconductor device, comprising:

• forming a device isolation layer on a semiconductor substrate, the device isolation layer including a cell array region defining a cell active region and a Mask-ROM region defining a Mask-ROM active region;
• forming a gate insulating layer on the semiconductor substrate;
• forming a photoresist pattern with an opening exposing portions of the gate insulating layer on the semiconductor substrate;
• forming a floating doped region within the cell active region and a channel doped region within the Mask-ROM active region with an ion implantation process that uses the photoresist pattern as a mask;
• etching the exposed gate insulating layer using the photoresist pattern as an etch mask to expose the floating doped region and the channel doped region;
• removing the photoresist pattern;
• forming a tunnel insulating layer on the exposed floating doped region and the exposed channel doped region;
• forming a sense line crossing the cell active region, a selection line crossing the cell active region, and a Mask-ROM gate crossing the Mask-ROM active region the semiconductor substrate where the tunnel insulating layer is formed.

A method of forming a semiconductor device, comprising:

• forming an isolation layer on a semiconductor substrate;
• forming a first insulating layer on the semiconductor substrate;
• forming a photoresist pattern on the first insulating layer, the photoresist pattern including an opening exposing portions of the first insulating layer and isolation layer;
• forming a floating doped region beneath the opening using the photoresist pattern;
• etching the first insulating layer using the photoresist pattern to form exposed portions;
• removing the photoresist pattern;
• and
• forming a second insulating layer on the exposed portions.

A method of fabricating a semiconductor device, comparing:

• forming a device isolation layer on a semiconductor substrate, the device isolation layer defining a cell active region and a Mask-ROM active region;
• forming a gate insulating layer on the semiconductor substrate;
• forming a first photoresist pattern on the gate insulating layer, the first photoresist pattern including an opening exposing portions of the gate insulating layer wherein said forming a first photoresist pattern further includes forming the first photoresist pattern so as to expose portions of the gate insulating layer within the cell active region, and to expose portions of the gate insulating layer and the device isolation layer within the Mask-ROM active region;
• forming a floating doped region within the cell active region under the opening by using the first photoresist pastern;
• exposing the floating doped region using the first photoresist pattern;
• removing the first photoresist pattern;
• and
• forming a tunnel insulating layer on the exposed floating doped region.