Non-volatile floating gate memory cell with floating gates formed as spacers, and an array thereof, and a method of manufacturing

An array of non-volatile memory cells, arranged in a plurality of rows and columns, said array comprising:

• a substantially single crystalline semiconductive substrate material of a first conductivity type;
• a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate material with each cell for storing a plurality of bits, and with each cell comprising:
• a first region of a second conductivity type, different from said first conductivity type in said material;
• a second region of said second conductivity type in said material, spaced apart from said first region;
• a channel region, having a first portion, a second portion and a third portion, connecting said first and second regions for the conduction of charges;
• a first dielectric adjacent to said channel region;
• a second dielectric adjacent to said first region;
• a third dielectric adjacent to said second region;
• a first floating gate of polysilicon adjacent to said first dielectric spaced apart from said first portion of said channel region, formed as a spacer, contiguous with and immediately adjacent to said second dielectric;
• a second floating gate of polysilicon adjacent to said first dielectric, spaced apart from said third portion of said channel region, formed as a spacer, contiguous with and immediately adjacent to said third dielectric;
• and
• a gate electrode capacitively coupled to said first floating gate, and said second floating gate, and spaced apart from said second portion of said channel region, said second portion of said channel region between said first portion and said third portion.
• wherein said cells in the same row have said gate electrode in common;
• wherein said cells in the same column have said first region in common, said second region in common, said second dielectric in common, and said third dielectric in common;
• and
• wherein said cells in adjacent columns have said first region in common.

A method of manufacturing a non-volatile memory cell in a substantially single crystalline semiconductive material of a first conductivity type, wherein said method comprising:

• forming a first region and a second region in said material, with said first region and said second region being of a second conductivity type, different from said first conductivity type, with a channel region for the conduction of charges connecting said first region and said second region;
• said channel region, having a first portion, a second portion and a third portion, with said second portion between said first portion and said third portion, with said first portion of said channel region adjacent to said first region and said third portion of said channel region adjacent to said second region;
• forming a first dielectric adjacent to said channel region;
• forming a second dielectric adjacent to said first region;
• forming a third dielectric adjacent to said second region;
• forming a first floating gate spacer contiguous with and immediately adjacent to said second dielectric, said first floating gate adjacent to said first dielectric and spaced apart from said first portion of said channel region;
• forming a second floating gate spacer contiguous with and immediately adjacent to said third dielectric, said second floating gate adjacent to said first dielectric and spaced apart from said third portion of said channel region;
• and
• forming a gate electrode, capacitively coupled to said first floating gate and said second floating gate, and spaced apart from said second portion of said channel region.

A method of manufacturing an array of non-volatile memory cells in a substantially single crystalline semiconductive material of a first conductivity type, wherein said array of non-volatile memory cells has a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate material, said method comprising:

• forming spaced apart first and second regions in said semiconductive substrate that are substantially parallel to one another and extend in a column direction, each of said first and second regions being of a second conductivity type, different from said first conductivity type, with a channel region therebetween for the conduction of charges connecting said first region and said second region;
• said channel region, having a first portion, a second portion and a third portion, with said first portion of said channel region adjacent to said first region and said third portion of said channel region adjacent to said second region, and with said second portion of the channel region between said first portion and said third portion;
• forming a first dielectric adjacent to said first region, said first dielectric extending in said column direction;
• forming a second dielectric adjacent to said second region, said second dielectric extending in said column direction;
• forming a third dielectric adjacent to said channel region;
• forming a first floating gate spacer, extending in said column direction, contiguous with and immediately adjacent to said first dielectric, adjacent to said third dielectric and spaced apart from said first portion of said channel region;
• forming a second floating gate spacer, extending in said column direction, contiguous with and immediately adjacent to said second dielectric, adjacent to said third dielectric and spaced apart from said third portion of said channel region;
• forming a plurality of spaced apart gate electrodes, each in a row direction, capacitively coupled to said first floating gate, said second floating gate, and spaced apart from said second portion of said channel region;
• and
• forming isolation regions between adjacent rows of gate electrodes.