Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

A method of manufacturing a semiconductor device, comprising:

• sequentially forming a gate insulation layer and a gate electrode on a substrate, an active region being defined on the substrate;
• forming a planarized layer on the substrate including the gate electrode;
• removing a first portion of the planarized layer, so that a top surface and upper portions of side surfaces of the gate electrode are exposed;
• selectively forming a silicon epitaxial layer on the top surface of the exposed gate electrode, wherein side surfaces of the silicon epitaxial layer are substantially aligned with the side surfaces of the gate electrode;
• removing a remaining portion of the planarized layer so that remaining portions of the side surfaces of the gate electrode are exposed;
• forming gate spacers along the substantially aligned side surfaces of the gate electrode and the silicon epitaxial layer;
• and
• forming a source/drain region on a surface portion of the active region corresponding to the gate electrode.