Chip scale package with open substrate
AssigneeST Assembly Test Services Ltd.
InventorsIl Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
Life of this patent
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Abstract
A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
Claims11
A method of manufacturing an integrated circuit package comprising:
- forming a substrate including:
- forming a core layer;
- forming a through opening and vias in the core layer;
- forming a first conductive layer on the core layer covering the through opening;
- forming a second conductive layer on the core layer opposite the first conductive layer, the second conductive layer formed in the through opening and in the vias contacting the first conductive layer;
- bonding an integrated circuit die to the second conductive layer and in the through opening;
- forming connections between the integrated circuit die and the second conductive layer;
- and
- encapsulating the integrated circuit die and the connections.
Dependencies are inferred from the claim text.