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US 7,006,515 B1Granted
Isochronous queue and buffer management
AssigneeOmneon Video Networks
InventorPauline Sai-Fun Yeung
Life of this patent
Estimating the term…
Abstract
A method of processing packets in a switch. A first queue is selected from at least three queues based on the cycle number (C) of a cycle and flushed at the start of cycle C. At least one isochronous packet is received over a bus during the cycle. The packet is placed in a second queue based on the cycle number.
Claims18
A method of processing packets in a switch comprising:
- selecting a first queue from at least three queues in a switch based on the cycle number (C) of a cycle;
- flushing the first queue at the start of the cycle;
- receiving at least one isochronous packet over a bus during the cycle;
- placing the packet in a second queue based on the cycle number.
1 more element
A switch in a network comprising:
- a buffer memory including at least three egress queues;
- and
- a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to direct the incoming isochronous packets into the egress queue number equal to the remainder of (C+2)/n wherein n is the number of queues in the switch.
A switch in a network comprising:
- a buffer memory including at least three egress queues;
- and
- a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to flush the egress queue number equal to the remainder of (C−1)/n wherein n is the number of queues in the switch.
A switch in a network comprising;
- a buffer memory including at least three egress queues;
- and
- a processor to direct incoming isochronous packets into one of the egress queues based on a cycle number of the switch and to flush another of the egress queues based on the cycle number wherein the processor is configured to transmit the isochronous packets from the egress queue number equal to the remainder of C/n wherein n is the number of queues in the switch.
Dependencies are inferred from the claim text.