# US 7,006,022 B1 · System and method for enhancing data correction capability using error information obtained from demodulation procedures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,006,022 B1
- Document ID: US7006022B1
- Status: Granted
- Kind: B1
- Application number: 10/961,214
- Filed: 2004-10-12
- Granted: 2006-02-28
- Earliest claimed: 2004-10-12
- Assignees: Cheertek Inc.
- Inventors: Sheng-Hung Wu
- Web page: https://patentgrep.com/patent/US7006022B1

## CPC

- G11B 20/18: Error detection or correction; Testing {, e.g. of drop-outs}
- G11B 20/10009: {Improvement or modification of read or write signals}
- H03M 13/6325: {Error control coding in combination with demodulation}
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A signal processing system that comprises a sampling device for converting a continuous signal into a discrete signal, a quantizing device for converting the discrete signal into a first bit stream, each bit in the bit stream having a first value, a detector for determining whether at least one bit in the first bit stream includes a second value different from the first value of the at least one bit, and a demultiplexer for converting a section of the first bit stream into a first modulation code, and converting a section of a second bit stream into a second modulation code, the second bit stream being formed by replacing the first value of the at least one bit in the first bit stream with the second value.

## Claims

### Claim 1

A signal processing system, comprising:
a sampling device for converting a continuous signal into a discrete signal;
a quantizing device for converting the discrete signal into a first bit stream, each bit in the bit stream having a first value;
a detector for determining whether at least one bit in the first bit stream includes a second value different from the first value of the at least one bit; and
a demultiplexer for converting a section of the first bit stream into a first modulation code, and converting a section of a second bit stream into a second modulation code, the second bit stream being formed by replacing the first value of the at least one bit in the first bit stream with the second value.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a digital filter between the sampling device and the quantizing device.

### Claim 3 (depends on 1)

The system of claim 1, wherein the quantizing device includes one of a digitizer circuit or a partial response maximum likelihood (“PRML”) circuit.

### Claim 4 (depends on 3)

The system of claim 3, wherein the detector determines whether an offset between a transition associated with the at least one bit and a corresponding clock edge provided by the sampling device is significant.

### Claim 5 (depends on 3)

The system of claim 3, wherein the detector determines whether an offset between an evaluation index of a selected path and an evaluation index of one of unselected paths is significant.

### Claim 6 (depends on 4)

The system of claim 4, wherein the offset is determined significant if the offset exceeds a threshold.

### Claim 7 (depends on 5)

The system of claim 5, wherein the offset is determined significant if the offset falls below a threshold.

### Claim 8 (depends on 1)

The system of claim 1, further comprising a demodulator for converting the first modulation code into a first symbol, and converting the second modulation code into a second symbol.

### Claim 9 (depends on 1)

The system of claim 1, further comprising a detector for detecting whether the first or second modulation code is modulated correctly.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a detector for detecting whether the run- length of the first or second modulation code is correct.

### Claim 11 (depends on 9)

The system of claim 9, further comprising a demodulator for providing a flag signal if the first or second modulation code is not correctly modulated.

### Claim 12 (depends on 10)

The system of claim 10, further comprising a demodulator for providing a flag signal if the run-length of the first or second modulation code is not correct.

### Claim 13

A signal processing system, comprising:
a sampling device for converting a continuous signal into a discrete signal transmitting in a waveform;
a digitizer circuit for converting the discrete signal into a first bit stream, each bit in the first bit stream having a first value, and detecting whether a transition occurs at an interception of the waveform of the discrete signal and a slicing level;
a detector for determining whether an offset between the transition and a corresponding clock edge provided by the sampling device is significant, and determining that a bit in the first bit stream associated with the transition includes a second value different from the first value of the bit if the offset is significant; and
a demultiplexer for converting a section of the first bit stream into a first modulation code, and converting a section of a second bit stream into a second modulation code, the second bit stream being formed by replacing the first value of the bit in the first bit stream with the second value.

### Claim 14 (depends on 13)

The system of claim 13, further comprising a phase detection circuit between the sampling device and the digitizer circuit.

### Claim 15 (depends on 13)

The system of claim 13, wherein the offset is determined significant if the offset exceeds a predetermined threshold.

### Claim 16 (depends on 13)

The system of claim 13, wherein the offset occurs in one of a temporal direction or a spatial direction.

### Claim 17 (depends on 13)

The system of claim 13, further comprising a detector for detecting whether the first modulation code or second modulation code matches a modulation code registered in a demodulation table.

### Claim 18 (depends on 13)

The system of claim 13, further comprising a detector for detecting whether the first modulation code or second modulation code meets a limit on run-length.

### Claim 19 (depends on 17)

The system of claim 17, further comprising a demodulator for providing a flag signal if the first or second modulation code does not match the modulation code registered in the demodulation table.

### Claim 20 (depends on 18)

The system of claim 18, further comprising a demodulator for providing a flag signal if the first or second modulation code does not meet the limit on run-length.

### Claim 21

A signal processing system, comprising:
a sampling device for converting a continuous signal into a discrete signal;
a partial response maximum likelihood (“PRML”) circuit for selecting a path of the most likelihood among a plurality of maximum likelihood paths each having an evaluation index, and converting the selected path into a first bit stream, each bit of the first bit stream having a first value;
a detector for determining whether an offset between the evaluation index of the selected path and the evaluation index of one of the unselected paths is significant, and determining that at least one bit in the first bit stream includes a second value different from the first value of the at least one bit if the offset is significant; and
a demultiplexer for converting a section of the first bit stream into a first modulation code, and converting a section of a second bit stream into a second modulation code, the second bit stream being formed by replacing the first value of the at least one bit in the first bit stream with the second value.

### Claim 22 (depends on 21)

The system of claim 21, further comprising a phase detection circuit between the sampling device and the PRML circuit.

### Claim 23 (depends on 21)

The system of claim 21, further comprising a detector for detecting whether the first or second modulation code is modulated correctly.

### Claim 24 (depends on 21)

The system of claim 21, further comprising a detector for detecting whether the run- length of the first or second modulation code is correct.

### Claim 25 (depends on 23)

The system of claim 23, further comprising a demodulator for providing a flag signal if the first or second modulation code is not correctly modulated.

### Claim 26 (depends on 24)

The system of claim 24, further comprising a demodulator for providing a flag signal if the run-length of the first or second modulation code is not correct.

### Claim 27 (depends on 21)

The system of claim 21, wherein the offset is determined significant if the offset falls below a-predetermined threshold.

### Claim 28

A method of signal processing, comprising:
converting a continuous signal into a discrete signal;
converting the discrete signal into a first bit stream, each bit in the first bit stream having a first value;
determining whether at least one bit in the first bit stream includes a second value different from the first value of the at least one bit;
forming a second bit stream by replacing the first value of the at least one bit in the first bit stream with the second value;
converting a section of the first bit stream into a first modulation code; and
converting a section of the second bit stream into a second modulation code.

### Claim 29 (depends on 28)

The method of claim 28, further comprising filtering the discrete signal.

### Claim 30 (depends on 28)

The method of claim 28, further comprising determining whether an offset between a transition associated with the at least one bit and a corresponding clock edge provided by the sampling device is significant.

### Claim 31 (depends on 28)

The method of claim 28, further comprising determining whether an offset between an evaluation index of a selected path and an evaluation index of one of unselected paths is significant.

### Claim 32 (depends on 30)

The method of claim 30, further comprising determining that the offset is significant if the offset exceeds a threshold.

### Claim 33 (depends on 31)

The method of claim 31, further comprising determining that the offset is significant if the offset falls below a threshold.

### Claim 34 (depends on 28)

The method of claim 28, further comprising detecting whether the first or second modulation code is modulated correctly.

### Claim 35 (depends on 28)

The method of claim 28, further comprising detecting whether the run-length of the first or second modulation code is correct.

### Claim 36 (depends on 28)

The method of claim 28, further comprising providing a flag signal indicating that the first or second modulation code includes an error.

### Claim 37

A method of signal processing, comprising:
converting a continuous signal into a discrete signal transmitting in a waveform;
converting the discrete signal into a first bit stream, each bit in the first bit stream having a first value;
detecting whether a transition occurs at an interception of the waveform of the discrete signal and a slicing level;
determining whether an offset between the transition and a corresponding clock edge provided by the sampling device is significant;
determining that a bit in the first bit stream associated with the transition includes a second value different from the first value of the bit if the offset is significant;
forming a second bit stream by replacing the first value of the bit in the first bit stream with the second value;
converting a section of the first bit stream into a first modulation code; and
converting a section of the second bit stream into a second modulation code.

### Claim 38 (depends on 37)

The method of claim 37, further comprising detecting whether the first modulation code or second modulation code matches a modulation code registered in a demodulation table.

### Claim 39 (depends on 37)

The method of claim 37, further comprising detecting whether the first modulation code or second modulation code meets a limit on run-length.

### Claim 40 (depends on 38)

The method of claim 38, further comprising providing a flag signal indicating that the first or second modulation code includes an error.

### Claim 41 (depends on 39)

The method of claim 39, further comprising providing a flag signal indicating that the first or second modulation code includes an error.

### Claim 42

A method of signal processing, comprising:
converting a continuous signal into a discrete signal;
selecting a path of the most likelihood among a plurality of maximum likelihood paths each having an evaluation index;
converting the selected path into a first bit stream, each bit of the first bit stream having a first value;
determining whether an offset between the evaluation index of the selected path and the evaluation index of one of the unselected paths is significant;
determining that at least one bit in the first bit stream includes a second value different from the first value of the at least one bit if the offset is significant;
forming a second bit stream by replacing the first value of the at least one bit in the first bit stream with the second value;
converting a section of the first bit stream into a first modulation code; and
converting a section of the second bit stream into a second modulation code.

### Claim 43 (depends on 42)

The method of claim 42, further comprising detecting whether the first modulation code or second modulation code matches a modulation code registered in a demodulation table.

### Claim 44 (depends on 42)

The method of claim 42, further comprising detecting whether the first modulation code or second modulation code meets a limit on run-length.

### Claim 45 (depends on 42)

The method of claim 42, further comprising providing a flag signal indicating that the first or second modulation code includes an error.