Method for fabricating programmable memory array structures incorporating series-connected transistor strings

An integrated circuit including a memory array having at least one memory level of memory cells, each memory level of said integrated circuit comprising:

• a plurality of channel stripes formed in a semiconductor layer deposited on a dielectric layer above the substrate, said channel stripes running in a first direction;
• a charge storage dielectric layer on the channel stripes;
• a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• heavily-doped regions in the channel stripes between the gate stripes, wherein adjacent heavily-doped regions do not contact each other beneath the gate stripes;
• and
• an interlevel dielectric layer above the gate stripes.

A method for manufacturing an integrated circuit having a three-dimensional memory array having more than one memory level of memory cells, said method comprising the steps of:

• forming a plurality of channel stripes on a dielectric layer above a substrate, said channel strips running in a first direction;
• forming a charge storage dielectric layer on the channel stripes;
• forming a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• forming heavily-doped regions in the channel stripes between the gate stripes by ion-implantation;
• forming an interlevel dielectric layer above the gate stripes;
• and
• repeating the aforementioned steps to form a second memory level.

An integrated circuit including a three-dimensional memory array having more than one memory level of memory cells, each memory level of said integrated circuit comprising:

• a plurality of channel stripes on a dielectric layer above a substrate, said channel stripes running in a first direction;
• a charge storage dielectric layer on the channel stripes;
• a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• ion-implanted heavily-doped regions in the channel stripes between the gate stripes;
• and
• an interlevel dielectric layer above the gate stripes.

A method for manufacturing an integrated circuit having a three-dimensional memory array having more than one memory level of memory cells, said method comprising the steps of:

• forming a plurality of channel stripes on a dielectric layer above a substrate, said channel stripes running in a first direction;
• forming a charge storage dielectric layer on the channel stripes;
• forming a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• forming in the channel stripes a single heavily-doped region between adjacent gate stripes;
• forming an interlevel dielectric layer above the gate stripes;
• and
• repeating the aforementioned steps to form a second memory level.

An integrated circuit including a three-dimensional memory array having more than one memory level of memory cells, each memory level of said integrated circuit comprising:

• a plurality of channel stripes on a dielectric layer above a substrate, said channel stripes running in a first direction;
• a charge storage dielectric layer on the channel stripes;
• a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• in the channel stripes, a single heavily-doped region between adjacent gate stripes;
• and
• an interlevel dielectric layer above the gate stripes.

A method for manufacturing an integrated circuit memory array, said method comprising the steps of:

• depositing a semiconductor layer on a dielectric layer above a substrate;
• forming a plurality of channel stripes in the semiconductor layer, said channel stripes running in a first direction, wherein adjacent channel stripes are electrically isolated from each other;
• forming a charge storage dielectric layer on the channel stripes;
• forming a plurality of gate strips on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• forming in the channel stripes a heavily-doped region between adjacent gate stripes;
• and
• forming an interlevel dielectric layer above the gate stripes.

An integrated circuit including a memory array having at least one memory level of memory cells, each memory level of said integrated circuit comprising:

• a plurality of channel stripes formed in a semiconductor layer deposited on a dielectric layer above a substrate, said channel stripes running in a first direction, wherein adjacent channel stripes are electrically isolated from each other;
• a charge storage dielectric layer on the channel stripes;
• a plurality of gate stripes on the charge storage dielectric layer, said gate stripes running in a second direction different than the first direction;
• in the channel stripes, a heavily-doped region between adjacent gate stripes;
• and
• an interlevel dielectric layer above the gate stripes.