Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring

A method of defining a power grid structure for use in an integrated circuit, wherein the power grid structure is comprised of power grid structure components and the integrated circuit is comprised of a plurality of layers having signal wiring that interconnects electronic and circuit components of the integrated circuit, the method comprising:

• receiving a first layer constraint specifying minimum and maximum areas that the power grid structure components can occupy on a first layer of the integrated circuit;
• receiving a power grid formula and an objective for the power grid formula;
• determining one or more dimensions or locations of the power grid structure components using the power grid formula, the objective for the power grid formula, and the first layer constraint;
• laying down the power grid structure components according to the one or more determined dimensions or locations to produce the power grid structure;
• performing global signal routing to define routes for signal wiring that interconnect the electronic and circuit components of the integrated circuit;
• testing whether the global signal routing was successful on the first layer;
• and
• modifying the first layer constraint upon determining that the global signal routing was not successful on the first layer.

A method of defining a power grid structure for use in an integrated circuit, wherein the power grid structure is comprised of a plurality of stripes, a plurality of rails, and a plurality of vias, wherein each stripe of the plurality of stripes is separated from another stripe by a distance defined by a stripe spacing width, each rail of the plurality of rails is separated from another rail by a distance defined by a rail spacing width, and the plurality of vias are used to connect the plurality of stripes to the plurality of rails, the method comprising:

• receiving a constraint requiring that the stripe spacing width be an integer multiple of the rail spacing width;
• receiving a power grid formula and an objective for the power grid formula;
• and
• determining one or more dimensions or locations of the plurality of stripes, the plurality of rails, or the plurality of vias using the power grid formula, the objective for the power grid formula, and the constraint.

A power grid structure for an integrated circuit, the power grid structure comprising:

• a plurality of stripes, each stripe being separated from another stripe by a distance defined by a stripe spacing width;
• a plurality of rails, each rail being separated from another rail by a distance defined by a rail spacing width;
• and
• a plurality of vias that connect the plurality of stripes to the plurality of rails, wherein the stripe spacing width is an integer multiple of the rail spacing width.

A power grid structure for an integrated circuit, the power grid structure having at least one design constraint that defines a minimum specification that the power grid structure must meet in order to be acceptable for use in the integrated circuit, the power grid structure comprising:

• a plurality of stripes;
• a plurality of rails;
• and
• a plurality of vias that connect the plurality of stripes to the plurality of rails, wherein the plurality of vias are arranged into a plurality of via arrays, each via array containing multiple vias and having a minimal area required for the power grid structure to meet the at least one design constraint.