US 7,003,747 B2Granted

Method of achieving timing closure in digital integrated circuits by optimizing individual macros

AssigneeInternational Business Machines Corporation

InventorsJun Zhou, David J. Hathaway, Chandramouli Visweswariah, Patrick M. Williams

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Abstract

Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Claims1

Dependent claims

A method of achieving the timing convergence of one of a digital integrated circuit and a functional unit of a digital integrated circuit comprising of the steps of:

partitioning a design into macros;
apportioning a timing and area budget to each of said macros;
creating an objective function for an optimization of the at least one of said macros having contributions from a plurality of primary output signals in said macro;
improving the timing characteristics of each of the at least one selected macros by attempting to minimize said objective function;
timing the overall design;
and
re-apportioning the timing and area budgets and repeating the said improving and timing steps until the required specifications are met;
and
in which the objective function comprises a summation of penalty contributions from each primary output siqnal, each of said penalty contributions being a non-decreasing penalty function of the the amount by which a timing requirement is violated in which said penalty function is a weighted and shifted exponential function of said violation amount.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/435,824Filed 12 May 2003
Published: US 2004/0230929 A118 Nov 2004
Granted: 21 Feb 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation