US 7,003,745 B2Granted

Performance modeling for circuit design

AssigneeCadence Design Systems, Inc.

InventorsPero Subasic, Rodney Phelps

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Abstract

Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

Claims22

Dependent claims

An automated integrated circuit design method comprising the steps of:

(a) inputting an initial layout of interconnected circuit devices that define a circuit;
(b) performing a plurality of circuit simulations for the circuit, with each circuit simulation performed for a unique layout of the circuit devices, with each circuit simulation generating a design point that includes a plurality of device variables for the circuit devices and a plurality of performance goals for the circuit, wherein each device variable and each performance goal has a value associated therewith;
(c) allocating the design points to a first subset of model building design points and a second subset of validation design points;
(d) utilizing a first model building technique to determine as a function of the model building design points a first circuit model for one of the performance goals;
(e) utilizing a second, different model building technique to determine as a function of the model building design points a second, different circuit model for the one performance goal;
(f) determining for each validation design point a value for the one performance goal as a function of said first circuit model and the values of the device variables of said validation design point;
(g) determining for each validation design point an error between the value of the one performance goal determined therefor in step (f) and the values of the corresponding performance goal of the validation design point;
(h) determining in connection with the first circuit model an average of the errors determined in step (g);
(i) determining for each validation design point a value for the one performance goal as a function of said second circuit model and the values of the device variables of said validation design point;
(j) determining for each validation design point an error between the value of the one performance goal determined therefor in step (i) and the value of the corresponding performance goal of the validation design point;
(k) determining in connection with the second circuit model an average of the errors determined in step (j);
(l) inputting a set of values of the device variables;
(m) processing the input set of values of the device variables with at least one of the first and second circuit models having the smallest average error associated therewith to determine at least one value for the one performance goal associated therewith;
and
(n) based on the value of the at least one performance goal determined in step (m), generating a layout of the circuit devices based on the values of the device variables input for said one performance goal in step (l).

12 more elements

A computer readable medium having stored thereon instructions which, when executed by a processor, cause the processor to perform the steps:

(a ) receive an initial layout of interconnected circuit devices that define a circuit;
(b) perform a plurality of circuit simulations for the circuit, with each circuit simulation performed for a unique layout of the circuit devices, with each circuit simulation generating a design point that includes a plurality of device variables for the circuit devices and a plurality of performance goals for the circuit, wherein each device variable and each performance goal has a value associated therewith;
(c) allocate the design points between a first subset of model building design points and a second subset of validation design points;
(d) determine a first circuit model and a second, different circuit model for one of the performance goals as a function of the model building design points;
(e) determine for each validation design point a value for the one performance goal as a function of said first circuit model and the values of the device variables of said validation design point;
(f) determine for each validation design point an error between the value of the one performance goal determined in step (e) and the value of the corresponding performance goal of the validation design point;
(g) determine in connection with the first circuit model an average of the errors determined in step (f);
(h) determine for each validation design point a value for the one performance goal as a function of said second circuit model and the values of the device variables of said validation design point;
(i) determine for each validation design point an error between the value of the one performance goal determined in step (h) and the value of the corresponding performance goal of the validation design point;
(j) determine in connection with the second circuit model an average of the errors determined in step (i);
(k) receive a set of device variable values;
(l) process the received set of device variable values with at least one of the first and second circuit models having the smallest error associated therewith to determine a value for the one performance goal associated therewith;
and
(m) based on the value of the one performance goal determined in step (l), generate a layout of the circuit devices based on the device variable values input in step (k).

11 more elements

An automated integrated circuit design method comprising the steps of:

(a) inputting an initial layout of interconnected circuit devices that define a circuit;
(b) performing a plurality of circuit simulations for the circuit, with each circuit simulation performed for a unique layout of the circuit devices, with each circuit simulation generating a design point that includes device variable values for the circuit devices and performance goal values for the circuit;
(c) determining a plurality of different circuit models for one of the performance goals as a function of a first subset of the design points;
(d) determining for each circuit model a value for the one performance goal as a function of the circuit model and the values of the device variables obtained from a second subset of the design points;
(e) determining for each circuit model errors between the value of the one performance goal determined in step (d) and values of corresponding performance goals obtained from the second subset of design points;
(f) inputting a set of device variable values;
(g) processing the input set of device variable values with at least one of the circuit models having the smallest error associated therewith to determine at least one value for the one performance goal;
(h) repeating steps (f) and (g) a plurality of times with a new set of device variable values input in each repetition;
and
(i) generating a layout of the circuit devices utilizing the device variable values processed in one of the repetitions of step (g).

7 more elements

Dependencies are inferred from the claim text.