Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
AssigneeZenasis Technologies, Inc.
InventorsDebashis Bhattacharya, Vamsi Boppana, Rajeev Murgai, Rabindra Roy
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Abstract
The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
Claims38
An automated method for designing an integrated circuit (IC) design-specific cell, said method comprising the steps of:
- receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
- mapping said design specification to a transistor-level representation of said design-specific cell;
- evaluating said transistor-level representation of said design-specific cell for meeting said design specification;
- and
- altering said transistor-level representation of said design-specific cell to meet said design specification.
A system for automatically designing an integrated circuit (IC) design-specific cell, said system comprising:
- an interface for receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
- a mapping process that maps said design specification to a transistor-level representation of said design-specific cell;
- an evaluating process that evaluates said transistor-level representation of said design-specific cell for determining whether said transistor-level representation of said IC meets said design specification;
- and
- an alteration process that alters said transistor-level representation of said design-specific cell to meet said design specification.
A design-specific cell produced by an automated integrated circuit (IC) design process, said IC design process comprises the steps of:
- receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
- mapping said design specification to a transistor-level representation of said design-specific cell,
- evaluating said transistor-level representation of said design-specific cell for meeting of said design specification;
- and
- altering said transistor-level representation of said design-specific cell to meet said design specification.
A storage medium having computer readable program instructions embodied therein for automatically designing an integrated circuit (IC) design-specific cell, said storage medium comprising:
- program instructions for receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
- program instructions for mapping said design specification to a transistor-level representation of said design-specific cell;
- program instructions for evaluating said transistor-level representation of said design-specific cell for satisfaction of said design specification;
- and
- program instructions for altering said transistor-level representation of said design-specific cell to meet said design specification.
Dependencies are inferred from the claim text.