Galois field multiply accumulator
AssigneeCisco Technology, Inc.
InventorAndrew J. Thurston
Life of this patent
Estimating the term…
Loading patent…
AssigneeCisco Technology, Inc.
InventorAndrew J. Thurston
Estimating the term…
An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. In the specific embodiment wherein the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.
A method of decoding an error-correction code in a data signal, comprising the steps of:
A method of determining an error polynomial for decoding a Bose-Chaudhuri-Hocquenghem (BCH) code, comprising the steps of:
A Galois field multiply accumulator comprising:
A decoder circuit comprising:
An OC-192 input/output card comprising:
Dependencies are inferred from the claim text.