System for facilitated analysis of PCI bus malfunction
AssigneeNEC Corporation
InventorMasao Ohwada
Life of this patent
Estimating the term…
Abstract
In a computer system, which makes an error detectable in case plural PCI target devices respond in one PCI cycle and the PCI protocol has become illicit, a processor 1 is connected over a PCI bus 10 to plural PCI devices a 100 to d 130, each of which activates corresponding target operating signal a 20 to d 50 respectively when operating as a PCI target device. The PCI bus monitor circuit 200 monitors the target address of a command executed on the PCI bus 10 and the target operating signals a 20 to d 50 from the plural PCI devices a 100 to d 130. If plural PCI target devices have responded for one PCI cycle, the PCI bus monitor circuit 200 sends an error report signal 210 to the processor unit 1.
Claims30
A system for enabling facilitated analysis of malfunctions in a computer device, said system comprising:
- a processor unit;
- a PCI bus;
- a plurality of PCI devices connected to said processor unit by said PCI bus, each PCI device, when operating as a PCI target device, activating a corresponding target operating signal;
- a PCI bus monitor circuit for monitoring a target address of a command from said processor unit to be executed on said PCI bus and monitoring the target operating signals from said plurality of PCI devices, said PCI bus monitor circuit sending an error report signal to said processor unit when plural PCI target devices respond to the command in one PCI cycle;
- and
- a target device selection circuit for specifying a PCI target device based on the base address values and size values of said plurality of PCI devices and on the target address.
A system for enabling facilitated analysis of malfunctions in a computer device, said system comprising:
- a processor unit;
- a PCI bus;
- a plurality of PCI devices connected to said processor unit by said PCI bus, each PCI device, when operating as a PCI target device, activating a corresponding target operating signal;
- a PCI bus monitor circuit for monitoring a target address of a command from said processor unit to be executed on said PCI bus and monitoring the target operating signals from said plurality of PCI devices, said PCI bus monitor circuit including a unit for resetting said PCI bus when plural PCI target devices respond to the command in one PCI cycle;
- and
- a target device selection circuit for specifying a PCI target device based on the base address values and size values of said plurality of PCI devices and on the target address.
A system for enabling facilitated analysis of malfunctions in a computer device, said system comprising:
- a PCI bus;
- a processor unit connected to said PCI bus, said processor unit activating a corresponding target operating signal when operating as a PCI target device;
- a plurality of PCI devices connected to said PCI bus, each of said PCI devices, when operating as a PCI target device, activating a corresponding target operating signal;
- a PCI bus monitor circuit for monitoring a target address of a command from said processor unit to be executed on said PCI bus and monitoring the target operating signals from said processor unit and from said plurality of PCI devices, said PCI bus monitor circuit sending an error report signal to said processor unit when plural PCI target devices have responded to the command in one PCI cycle;
- and
- a target device selection circuit for specifying a target device based on the base address values and size values of said plurality of PCI devices and on the target address.
A system for enabling facilitated analysis of malfunctions in a computer device, said system comprising:
- a PCI bus;
- a processor unit connected to said PCI bus, said processor unit activating a corresponding target operating signal when operating as a PCI target device;
- a plurality of PCI devices connected to said PCI bus, each of said PCI devices, when operating as a PCI target device, activating a corresponding target operating signal;
- a PCI bus monitor circuit for monitoring a target address of a command from said processor unit to be executed on said PCI bus and monitoring the target operating signals from said plurality of PCI devices, said PCI bus monitor circuit including a unit for resetting said PCI bus when plural PCI target devices respond to the command in one PCI cycle;
- and
- a target device selection circuit for specifying a PCI target device based on the base address values and size values of said processor unit and said plurality of PCI devices and on the target address.
A method of facilitated analysis of malfunctions in a computer device which includes a processor unit, a PCI bus, and a plurality of PCI devices connected to the processor unit by the PCI bus, the method comprising:
- each PCI device, when operating as a PCI target device, activating a corresponding target operating signal;
- monitoring a target address of a command from said processor unit to be executed on the PCI bus;
- monitoring the target operating signals from the plurality of PCI devices;
- and
- sending an error report signal to the processor unit when plural PCI target devices respond to the command in one PCI cycle,
- wherein monitoring the target operating signals comprises specifying a PCI target device based on stored base address values and size values of the plurality of PCI devices and on a stored target address.
A method of facilitated analysis of malfunctions in a computer device which includes a processor unit, a PCI bus, and a plurality of PCI devices connected to the processor unit by the PCI bus, the method comprising:
- at each PCI device, when operating as a PCI target device, activating a corresponding target operating signal;
- monitoring a target address of a command from said processor unit to be executed on the PCI bus;
- monitoring the target operating signals from the plurality of PCI devices;
- and
- resetting the PCI bus when plural PCI target devices respond to the command in one PCI cycle,
- wherein monitoring the target operating signals comprises specifying a PCI target device based on stored base address values and size values of the plurality of PCI devices and on a stored target address.
A method of facilitated analysis of malfunctions in a computer device which includes a processor unit, a PCI bus, and a plurality of PCI devices connected to said processor unit by the PCI bus, the method comprising:
- activating a corresponding target operating signal when the processor unit is operating as a PCI target device;
- activating, by each PCI device when operating as a PCI target device, a corresponding target operating signal;
- monitoring a target address of a command from the processor unit to be executed on the PCI bus;
- monitoring the target operating signals from the processor unit and from the plurality of PCI devices;
- and
- sending an error report signal to the processor unit when plural PCI target devices have responded to the command for one PCI cycle,
- wherein monitoring the target operating signals comprises specifying a PCI target device based on stored base address values and size values of the plurality of PCI devices and on a stored target address.
A method of facilitated analysis of malfunctions in a computer device which includes a processor unit, a PCI bus, and a plurality of PCI devices connected to said processor unit by the PCI bus, the method comprising:
- activating a corresponding target operating signal when the processor unit is operating as a PCI target device;
- activating, by each PCI device when operating as a PCI target device, a corresponding target operating signal;
- monitoring a target address of a command from the processor unit to be executed on the PCI bus;
- monitoring the target operating signals from the plurality of PCI devices;
- and
- resetting the PCI bus when plural PCI target devices respond to the command in one PCI cycle,
- wherein monitoring the target operating signals comprises specifying a PCI target device based on stored base address values and size values of the processor unit and the plurality of PCI devices and on a stored target address.
Dependencies are inferred from the claim text.