Interface circuit

An interface circuit comprising:

• a clock signal;
• a first phase locked loop coupled to the clock signal line and generating a reference clock signal;
• a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals;
• and
• a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit,
• wherein the second phase locked loop further generates a low pass filter signal, and wherein the data transceiver is further coupled to receive the low pass filter signal.

An interface circuit comprising:

• interface core logic;
• a clock signal;
• a first phase locked loop coupled to the clock signal and generating a reference clock signal, the first phase locked loop including one or more reference delay elements;
• a second phase locked loop coupled to the reference clock signal and generating one or more phase shifted reference clock signals;
• and
• a data transceiver circuit coupled between the interface core logic and a node, the data transceiver circuit receiving at least one of the clock signal, the reference clock signal, or the one or more phase shifted reference clock signals for controlling the flow of data between the interface core logic and the node, wherein the data transceiver circuit includes one or more delay elements corresponding to at least one of the one or more reference delay elements.

A method of controlling the flow of data between a first circuit and a second circuit comprising:

• generating a first reference clock signal from an input clock signal using a first phase locked loop;
• generating one or more phase shifted reference clock signals from the first reference clock signal using a second phase locked loop;
• receiving one or more of the phase shifted reference clock signals in a data transceiver circuit for controlling the flow of data between said first and second circuits;
• and
• generating a delayed clock signal in a feedback loop of the first phase locked loop,
• wherein a time delay between the delayed clock signal and the input clock signal is approximately equal to a time delay of a delay element in an input path of the data transceiver circuit.

A method of controlling the flow of data between a first circuit and a second circuit comprising:

• generating a first reference clock signal from an input clock signal using a first phase locked loop;
• generating one or more phase shifted reference clock signals from the first reference clock signal using a second phase locked loop;
• receiving one or more of the phase shifted reference clock signals in a data transceiver circuit for controlling the flow of data between said first and second circuits;
• and
• generating a delayed clock signal in a feedback loop of the first phase locked loop,
• wherein a time delay between the delayed clock signal and the first reference clock signal is approximately equal to a time delay of one or more delay elements in an output path of the data transceiver circuit.

A microprocessor memory interface circuit comprising:

• a first phase locked loop coupled to a clock signal line and generating a reference clock signal;
• a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals;
• and
• a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit,
• wherein the first phase locked loop includes a feedback loop and at least one reference delay element in the feedback loop, and the data transceiver circuit includes a delay element, and wherein time delays of the delay element and reference delay element are approximately equal.