US 7,003,652 B2Granted

Restarting translated instructions

AssigneeArm Limited

InventorsEdward Colles Nevill, Andrew Christopher Rose

Life of this patent

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Abstract

A processing system has a processor core executing instructions of a first instruction set and an instruction translator for generating translator output signals corresponding to one or more instructions of the first instruction set so as to emulate instructions of a second instruction set. The instruction translator provides translator output signals specifying operations that are arranged so that the input variables to an instruction of the second instruction set are not changed until the final operation emulating that instruction is executed. An interrupt handler services an interrupt after execution of an operation of the instructions of the first instruction set. Arranging the translated sequences of instructions such that the input state is not altered until the final instruction is executed has the result that processing may be restarted after the interrupt either by rerunning the complete emulation if the final operation had not started when the interrupt occurred, or by running the next instruction from the second instruction set if the final operation had started when the interrupt occurred.

Claims17

Dependent claims

An apparatus for processing data, said apparatus comprising:

(i) a processor core operable to execute operations as specified by instructions of a first instruction set;
(ii) an instruction translator operable to translate instructions of a second instruction set into translator output signals corresponding to instructions of said first instruction set, at least one instruction of said second instruction set specifying an operation to be executed using one or more input variables;
(iii) an interrupt handler responsive to an interrupt signal to interrupt execution of operations corresponding to instructions of said first instruction set after completion of execution of any currently executing operation;
and
(iv) restart logic for restarting execution after said interrupt;
wherein
(v) said instruction translator is operable to generate a sequence of one or more sets of translator output signals corresponding to instructions of said first instruction set to represent said at least one instruction of said second instruction set, each sequence being such that no change is made to said one or more input variables until a final operation within said sequence is executed;
and
(vi) after occurrence of an interrupt during execution of a sequence of operations representing said at least one instruction of said second instruction set:
(a) if said interrupt occurred prior to starting execution of a final operation in said sequence, then said restart logic restarts execution at a first operation in said sequence;
and
(b) if said interrupt occurred after starting execution of a final operation in said sequence, then said restart logic restarts execution at a next instruction following said sequence.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/887,559Filed 25 Jun 2001
Priority: GB 00244025 Oct 2000
Published: US 2002/0066003 A130 May 2002
Granted: 21 Feb 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 9/4843
Task transfer initiation or dispatching: by program, e.g. task dispatcher, supervisor, operating system
G06F 9/30101
Register arrangements: special purpose registers
G06F 9/30134
Organisation of register space, e.g. banked or distributed register file: register stacks; shift registers
G06F 9/30149
Instruction analysis, e.g. decoding, instruction word fields: of variable length instructions