Method for prioritizing operations within a pipelined microprocessor based upon required results

An explicit parallelism architecture processor comprising a set of different latency executive units, a register file with a set of write ports to write the operation execution results and a bypass to transfer the operation execution results to the following operations as operands before they are actually written into the register file, wherein:

• a set of short latency executive units has equal latencies due to the introduction of additional stages in the shortest ones, which ensures the issue order of the operation execution results;
• a set of long and undefined latency executive units has a means for canceling the result write into the register file for operations having a WAW hazard and issued first for execution, in this case the write inhibition is performed after the operations coming for execution are checked for the absence of precise exception, wherein the means for canceling the result write into the register file for operations having a WAW hazard and issued first for execution comprises:
• an address result path of executive pipeline, comprising the write addresses into the register file of all operations contained in the execution units;
• comparators of the register file write addresses of the first stage after checking for precise exception absence of all executive units with write addresses of all the following stages of all executive units;
• and
• a reset circuit of a validate bit of the write address into the register file by the comparison results obtained by said comparators;
• a bypass control unit comprises a means for inhibiting the issue into the bypass of the results of operations having the WAW hazard and issued first for execution;
• and
• stages of the short latency executive units added for latency aligning are connected to the bypass, which maintains a fast access to the results of the instructions before they are written into the register file.

An explicit parallelism architecture processor comprising a set of different latency executive units, a register file with a set of write ports to write the operation execution results and a bypass to transfer the operation execution results to the following operations as operands before they are actually written into the register file, wherein:

• a set of short latency executive units has equal latencies due to the introduction of additional stages in the shortest ones, which ensures the issue order of the operation execution results;
• a set of long and undefined latency executive units has a means for canceling the result write into the register file for operations having a WAW hazard and issued first for execution, in this case the write inhibition is performed after the operations coming for execution are checked for the absence of precise exception;
• a bypass control unit comprises a means for inhibiting the issue into the bypass of the results of operations having the WAW hazard and issued first for execution, wherein the means for inhibiting the result issue into the bypass for operations having a WAW hazard and issued first for execution comprises:
• an address result path of the executive pipeline, comprising write addresses into the register file of all operations available in the executive units;
• comparators of operand addresses of all operations issued into the executive units with all write addresses into the register file of all stages of the execution units, used to control the results issue into the bypass;
• and
• comparators of register file write addresses of all stages of the executive units and write addresses of all the following stages, used to inhibit the issue of the results into the bypass;
• and
• stages of the short latency executive units added for latency aligning are connected to the bypass, which maintains a fast access to the results of the instructions before they are written into the register file.