Control forwarding in a pipeline digital processor
AssigneeHitachi, Ltd.
InventorSivaram Krishnan
Life of this patent
Estimating the term…
Abstract
A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a target instruction, are made available for selection by a control bypass signal that is generated during decode of the branch instruction.
Claims9
A method of selecting one of two branch instruction paths for application to an execution unit of a digital processor in response to a branch instruction, a one and another of the two branch instruction paths having as a first instruction a target instruction and a next inline instruction, respectively, the method including the steps of:
- storing target instruction and the next inline instruction, and at least partially decoding the target instruction;
- producing a selection signal from decode of a branch instruction;
- using the selection signal to select the target instruction or the next inline instruction;
- and
- applying the selected target instruction or next inline instruction to the execution unit.
A digital processor operating to decode and execute instructions, including compare and branch instructions, the digital processor comprising:
- storage for holding a target instruction and a next in-line instruction;
- a selector element coupled to the storage to receive the target instruction and the next in-line instruction;
- an execution pipeline having a decode stage to receive and decode the compare instruction to produce a branch condition and then receive and at least partially decode the branch instruction to assert a bypass control signal that is coupled to the multiplexer to select the target instruction or the next in-line instruction for input to the execution pipeline when the condition is true;
- and
- wherein a first conditional branch instruction, when applied to the decode stage, causes the bypass control signal to be asserted.
A digital processor operating to decode and execute instructions, including compare and branch instructions, the digital processor comprising:
- a first storage for holding a target instruction;
- a second storage for holding a next in-line instruction;
- a multiplexer having inputs to receive the first and second storage;
- an execution unit to receive and decode the compare instruction to compare at least two values identified by the compare instruction to produce a true condition if the compare is successful and then to receive the branch instruction to assert a bypass control signal that is coupled to the multiplexer to select the target instruction for input to the pipeline when the condition is true, the execution unit including a plurality of pipeline stages including an decode stage to decode the instructions;
- and
- wherein a first conditional branch instruction, when applied to the decode stage, causes the bypass control signal to be asserted.
A digital processor operating to decode and execute instructions, including compare and branch instructions, the digital processor comprising:
- a first storage for holding a target instruction;
- a second storage for holding a next in-line instruction;
- a multiplexer having inputs to receive the first and second storage;
- an execution unit to receive and decode the compare instruction to compare at least two values identified by the compare instruction to produce a true condition if the compare is successful and then to receive the branch instruction to assert a bypass control signal that is coupled to the multiplexer to select the target instruction for input to the pipeline when the condition is true;
- and
- a pre-decode unit to couple the first and second storage to the multiplexer to perform predecoding on the target instruction and the next in-line instruction.
Dependencies are inferred from the claim text.