Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU

A computer system, comprising:

• an input device;
• and
• a processor coupled to said and receiving input signals from said input device, said processor Including:
• an allocation unit that assigns identifier numbers to instructions, said instructions selected from a group consisting of load instructions and store instructions;
• an instruction queue into which said instructions are stored, said instruction queue coupled to said allocation unit;
• a second queue into which instructions from said instruction queue are written after execution and pending retirement, said second queue having a plurality of entries for storing instructions and their identifier numbers;
• and
• allocation logic that allocates entries in the second queue to instructions from the instruction queue based on a demand for said entries by at least one thread processing unit (“TPU”), said demand updated during processor operation.

A multithreaded processor having logic organized as a plurality of thread processing units (“TPUs”), each TPU capable of running a process, said processor comprising:

• a store number (“SNUM”) allocation unit which assigns SNUMs to store instructions in each of a plurality of TPUs, an SNUM comprising a unique value assigned to each store instruction in a TPU, and each TPU having its own set of unique SNUMs;
• an instruction queue coupled to said SNUM allocation unit, and store instructions are stored in said instruction queue;
• a multi-entry store queue into which a store instruction associated with a TPU is sent from said instruction queue when an entry is allocated to the TPU;
• allocation logic coupled to said SNUM allocation unit and said store queue, said allocation logic determining whether each TPU has a need for entries in the store queue for store instructions associated with the TPU currently being held in the instruction queue by comparing the most recently assigned SNUM for each TPU to an adjustable threshold value.

A multithreaded processor having logic organized as a plurality of thread processing units (“TPUs”), each TPU capable of running a process, said processor comprising:

• a load number (“LNUM”) allocation unit which assigns LNUMs to load instructions in each of a plurality of TPUs, an LNUM comprising a unique value assigned to each load instruction in a TPU, and each TPU having its own set of unique LNUMs;
• an instruction queue coupled to said LNUM allocation unit, and load instructions are stored in said instruction queue;
• a multi-entry load queue into which a load instruction associated with a TPU is sent from said instruction queue when an entry is allocated to the TPU;
• allocation logic coupled to said LNUM allocation unit and said load queue, said allocation logic determining whether each TPU has a need for entries in the load queue for load instructions associated with the TPU currently being held in the instruction queue by comparing the most recently assigned LNUM for each TPU to an adjustable threshold value.

A method of dynamically allocating resources in a multithreaded processor implementing a plurality of thread processor units (“TPUs”), each TPU capable of running a process, said method comprising:

• determining a demand for a processor resource on behalf of each TPU, wherein said determining a demand includes comparing an instruction identifier value to a high water mark value for each TPU, said high water mark value representing the youngest instruction in the processor that is allowed to issue;
• determining whether the resource is available to be allocated to a TPU;
• if multiple TPUs have demand for the resource, arbitrating among the TPUs for allocation of the resource;
• and
• allocating the resource to the winner of said arbitration.

A processor, comprising:

• an allocation unit that assigns identifier numbers to instructions, said instructions selected from a group consisting of load instructions and store instructions;
• an instruction queue into which said instructions are stored, said instruction queue coupled to said allocation unit;
• a second queue into which instructions from said instruction queue are written pending execution, said second queue having a plurality of entries for storing instructions and their identifier numbers;
• and
• means for causing entries in the second queue to be allocated to instructions from the instruction queue based on a demand for said entries by at least one processing unit, said demand updated during processor operation.

A processor comprising:

• an allocation unit that assigns identifier numbers to instructions;
• a first storage area coupled to said allocation unit into which a plurality of instructions are stored;
• a second storage area into which instructions from said first storage area are written, said second storage area having a plurality of entries for storing instructions and their identifier numbers;
• and
• allocation logic that causes entries in the second storage area to be allocated to instructions from said first storage area based on demand for said entries by at least one processing unit, said demand updated d u ring processor operations.

A processor comprising:

• an allocation unit that assigns identifier numbers to instructions;
• a first storage area coupled to said allocation unit into which a plurality of instructions are stored;
• a second storage area into which values which identify instructions from said first storage area are stored;
• allocation logic that causes entries in the second storage area to be allocated to instructions from said first storage area based on demand for said entries by at least one processing unit, said demand updated during processor operations.