Burst counter controller and method in a memory device operable in a 2-bit prefetch mode

A dynamic random access memory (“DRAM”), comprising:

• an even array of memory cells arranged in rows and columns;
• an odd array of memory cells arranged in rows and columns;
• a row decoder coupled to receive a row address and being operable to activate a row of memory cells corresponding to the row address;
• a column address decoder coupled to receive a column address and to select a column of memory cells in each array corresponding to the column address;
• a data path coupled between the memory arrays and a data bus;
• a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands;
• a pre-settable burst counter changing count responsive to a clock signal, the burst counter having a count input receiving all but the least significant bit of a column address from which the counter increments or decrements, the burst counter further including a counter control input terminal receiving a counter control signal having a first value causing the burst counter to increment responsive to the clock signal or a second value causing the burst counter to decrement responsive to the clock signal;
• and
• a counter control circuit receiving a mode signal having a first value indicative of a serial mode of operation and a second value indicative of an interleave mode of operation, the counter control circuit further receiving the least significant bit (“LSB”) and the next to least significant bit (“NLSB”) of the column address, the counter control circuit being operable to decode a value of “1” for the LSB and the first value of the mode signal and to generate the second value of the counter control signal responsive thereto, to decode a value of “1” for the NLSB and the second value of the mode signal and to generate the second value of the counter control signal responsive thereto, and to generate the first value of the counter control signal responsive to decoding other values of the LSB, NLSB and the mode signal.

A dynamic random access memory (“DRAM”) operable in a serial mode, the DRAM, comprising:

• an even array of memory cells arranged in rows and columns;
• an odd array of memory cells arranged in rows and columns;
• a row decoder coupled to receive a row address and being operable to activate a row of memory cells corresponding to the row address;
• a column address decoder coupled to receive a column address and to select a column of memory cells in each array corresponding to the column address;
• a data path coupled between the memory arrays and a data bus;
• a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands;
• and
• a pre-settable burst counter changing count responsive to a clock signal, the burst counter having a count input receiving all but the least significant bit of a column address from which the counter increments or decrements, the burst counter further including a counter control input terminal receiving a counter control signal having a first value causing the burst counter to increment responsive to the clock signal or a second value causing the burst counter to decrement responsive to the clock signal;
• and
• a counter control circuit receiving the least significant bit (“LSB”) of the column address, the counter control circuit being operable to generate the second value of the counter control signal responsive to a value of “1” for the LSB, and to generate the first value of the counter control signal responsive to a value of “0” for the LSB.

A computer system, comprising:

• computer circuitry operable to perform computing functions;
• at least one input device coupled to the computer circuitry;
• at least one output device coupled to the computer circuitry;
• at least one data storage devices coupled to the computer circuitry;
• and
• a dynamic random access memory, comprising
• an even array of memory cells arranged in rows and columns;
• an odd array of memory cells arranged in rows and columns;
• a row decoder coupled to receive a row address and being operable to activate a row of memory cells corresponding to the row address;
• a column address decoder coupled to receive a column address and to select a column of memory cells in each array corresponding to the column address;
• a data path coupled between the memory arrays and a data bus;
• a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands;
• a pre-settable burst counter changing count responsive to a clock signal, the burst counter having a count input receiving all but the least significant bit of a column address from which the counter increments or decrements, the burst counter further including a counter control input terminal receiving a counter control signal having a first value causing the burst counter to increment responsive to the clock signal or a second value causing the burst counter to decrement responsive to the clock signal;
• and
• a counter control circuit receiving a mode signal having a first value indicative of a serial mode of operation and a second value indicative of an interleave mode of operation, the counter control circuit further receiving the least significant bit (“LSB”) and the next to least significant bit (“NLSB”) of the column address, the counter control circuit being operable to decode a value of “1” for the LSB and the first value of the mode signal and to generate the second value of the counter control signal responsive thereto, to decode a value of “1” for the NLSB and the second value of the mode signal and to generate the second value of the counter control signal responsive thereto, and to generate the first value of the counter control signal responsive to decoding other values of the LSB, NLSB and the mode signal.

A computer system, comprising:

• computer circuitry operable to perform computing functions;
• at least one input device coupled to the computer circuitry;
• at least one output device coupled to the computer circuitry;
• at least one data storage devices coupled to the computer circuitry;
• and
• a dynamic random access memory operable in a serial mode, the dynamic random access memory comprising
• an even array of memory cells arranged in rows and columns;
• an odd array of memory cells arranged in rows and columns;
• a row decoder coupled to receive a row address and being operable to activate a row of memory cells corresponding to the row address;
• a column address decoder coupled to receive a column address and to select a column of memory cells in each array corresponding to the column address;
• a data path coupled between the memory arrays and a data bus;
• a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands;
• and
• a pre-settable burst counter changing count responsive to a clock signal, the burst counter having a count input receiving all but the least significant bit of a column address from which the counter increments or decrements, the burst counter further including a counter control input terminal receiving a counter control signal having a first value causing the burst counter to increment responsive to the clock signal or a second value causing the burst counter to decrement responsive to the clock signal;
• and
• a counter control circuit receiving the least significant bit (“LSB”) of the column address, the counter control circuit being operable to generate the second value of the counter control signal responsive to a value of “1” for the LSB and to generate the first value of the counter control signal responsive to a value of “0” for the LSB.

A method of burst-mode addressing a 2-bit prefetch memory device operable in either a serial mode or an interleave mode, comprising:

• in the serial mode, incrementing a column address from a starting column address when a least significant bit (“LSB”) of the starting column address is a logic “0”;
• in the serial mode, decrementing a column address from the starting column address when the LSB of the starting column address is a logic “1”;
• in the interleave mode, incrementing a column address from the starting column address when a next to least significant bit (“NLSB”) of the starting column address is a logic “0”;
• and
• in the interleave mode, decrementing a column address from the starting column address when the NLSB of the starting column address is a logic “1”.