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US 7,003,638 B2Granted
Memory bus interface for use in a peripheral device
AssigneeStandard Microsystems Corporation
InventorsPaul M. Brant, John E. Stone, III
Life of this patent
Estimating the term…
Abstract
A peripheral device may include an interface configured to interface to a memory bus and a functional unit coupled to the interface and configured to perform a peripheral device function on data accessed by the interface. The interface may be configured to perform a data access in response to memory control, address, and data signals on the memory bus. The functional unit may be configured to perform various peripheral device functions such as data communication functions, video functions, printing functions, mass storage functions, and human interface controller functions.
Claims53
An interface for use with a peripheral device, the interface comprising:
- a memory bus interface configured to receive memory control, address, and data signals on a memory bus, wherein the memory bus interface is operable to decode commands from the memory control signals;
- a device interface coupled to the memory bus interface, wherein the device interface is configured to communicate data to a functional unit in the peripheral device and/or to the memory bus in response to the memory bus interface receiving memory control, address, and data signals on the memory bus, and according to the commands decoded from the memory control signals.
A peripheral device, comprising:
- an interface configured to interface to a memory bus, and further configured to decode commands from memory control signals on the memory bus, wherein the interface is operable to perform a data access in response to memory control, address, and data signals on the memory bus and according to the commands decoded from the memory control signals;
- and
- a functional unit coupled to the interface and configured to perform one or more functions associated with the peripheral device, on the data accessed by the interface.
A peripheral device, comprising:
- an interface configured to interface to a memory bus, wherein the interface is configured to receive memory control, address, and data signals on the memory bus, and is operable to decode commands from the memory control signals received on the memory bus;
- and
- a functional unit coupled to the interface, wherein the functional unit is configured to perform functions associated with the peripheral device;
- wherein the interface is configured to provide data to the functional unit in response to receiving the memory control, address, and data signals on the memory bus, and according to the commands decoded from the memory control signals received on the memory bus;
- wherein the peripheral device is operable to couple to the memory bus via the interface and to be accessed as a memory device.
2 more elements
A computer system, comprising:
- a memory controller;
- a memory bus coupled to the memory controller;
- memory coupled to the memory bus;
- a peripheral device coupled to the memory bus;
- wherein the peripheral device is configured to respond to memory control signals and address signals generated by the memory controller on the memory bus, wherein the peripheral device is operable to decode commands from the memory control signals, and to respond to the memory control signals and address signals according to the commands.
2 more elements
A method, comprising:
- generating memory control signals and address signals on a memory bus;
- a peripheral device coupled to the memory bus receiving the memory control signals and address signals;
- the peripheral device decoding commands from the memory control signals;
- in response to said receiving, the peripheral device performing a data access indicated by the memory control signals and address signals, and according to the commands;
- the peripheral device performing a function associated with the peripheral device on data accessed by said performing.
2 more elements
An interface for use with a peripheral device, the interface comprising:
- a memory bus interface configured to receive memory control, address, and data signals on a memory bus, wherein the memory bus interface is operable to access a memory mapped control and configuration register in response to an address corresponding to the memory mapped control and configuration register being indicated by address signals on the memory bus;
- and
- a device interface coupled to the memory bus interface, wherein the device interface is configured to communicate data to a functional unit in the peripheral device in response to the memory bus interface receiving memory control, address, and data signals on the memory bus.
A computer system, comprising:
- a memory controller;
- a memory bus coupled to the memory controller;
- memory coupled to the memory bus;
- and
- a peripheral device coupled to the memory bus;
- wherein the peripheral device is configured to respond to memory control signals and address signals generated by the memory controller on the memory bus, and wherein the peripheral device is configured to participate in burst transfers of data on the memory bus;
- and
- wherein in response to receiving memory control signals initiating a burst write command on the memory bus, the peripheral device is configured to receive a burst of data in successive burst transfers on the memory bus and to store the burst of data to a memory mapped structure included in the peripheral device.
5 more elements
A computer system, comprising:
- a memory controller;
- a memory bus coupled to the memory controller;
- memory coupled to the memory bus;
- a peripheral device coupled to the memory bus;
- wherein the peripheral device is configured to respond to memory control signals and address signals generated by the memory controller on the memory bus, and wherein the peripheral device is operable to access a memory mapped control and configuration register included in the peripheral device in response to an address corresponding to the memory mapped control and configuration register being indicated by address signals on the memory bus.
2 more elements
Dependencies are inferred from the claim text.